llvm-6502/test/CodeGen/X86/lzcnt.ll
Chandler Carruth acc068e873 Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the
X86ISelLowering C++ code. Because this is lowered via an xor wrapped
around a bsr, we want the dagcombine which runs after isel lowering to
have a chance to clean things up. In particular, it is very common to
see code which looks like:

  (sizeof(x)*8 - 1) ^ __builtin_clz(x)

Which is trying to compute the most significant bit of 'x'. That's
actually the value computed directly by the 'bsr' instruction, but if we
match it too late, we'll get completely redundant xor instructions.

The more naive code for the above (subtracting rather than using an xor)
still isn't handled correctly due to the dagcombine getting confused.

Also, while here fix an issue spotted by inspection: we should have been
expanding the zero-undef variants to the normal variants when there is
an 'lzcnt' instruction. Do so, and test for this. We don't want to
generate unnecessary 'bsr' instructions.

These two changes fix some regressions in encoding and decoding
benchmarks. However, there is still a *lot* to be improve on in this
type of code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 10:55:54 +00:00

63 lines
1.3 KiB
LLVM

; RUN: llc < %s -march=x86-64 -mattr=+lzcnt | FileCheck %s
declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone
declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone
declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
define i8 @t1(i8 %x) nounwind {
%tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 false )
ret i8 %tmp
; CHECK: t1:
; CHECK: lzcntw
}
define i16 @t2(i16 %x) nounwind {
%tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 false )
ret i16 %tmp
; CHECK: t2:
; CHECK: lzcntw
}
define i32 @t3(i32 %x) nounwind {
%tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 false )
ret i32 %tmp
; CHECK: t3:
; CHECK: lzcntl
}
define i64 @t4(i64 %x) nounwind {
%tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 false )
ret i64 %tmp
; CHECK: t4:
; CHECK: lzcntq
}
define i8 @t5(i8 %x) nounwind {
%tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 true )
ret i8 %tmp
; CHECK: t5:
; CHECK: lzcntw
}
define i16 @t6(i16 %x) nounwind {
%tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 true )
ret i16 %tmp
; CHECK: t6:
; CHECK: lzcntw
}
define i32 @t7(i32 %x) nounwind {
%tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true )
ret i32 %tmp
; CHECK: t7:
; CHECK: lzcntl
}
define i64 @t8(i64 %x) nounwind {
%tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 true )
ret i64 %tmp
; CHECK: t8:
; CHECK: lzcntq
}