llvm-6502/test/CodeGen/ARM64/2012-05-07-DAGCombineVectorExtract.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

21 lines
421 B
LLVM

; RUN: llc < %s -march=arm64 | FileCheck %s
define i32 @foo(<4 x i32> %a, i32 %n) nounwind {
; CHECK-LABEL: foo:
; CHECK: fmov w0, s0
; CHECK-NEXT: ret
%b = bitcast <4 x i32> %a to i128
%c = trunc i128 %b to i32
ret i32 %c
}
define i64 @bar(<2 x i64> %a, i64 %n) nounwind {
; CHECK-LABEL: bar:
; CHECK: fmov x0, d0
; CHECK-NEXT: ret
%b = bitcast <2 x i64> %a to i128
%c = trunc i128 %b to i64
ret i64 %c
}