llvm-6502/test/CodeGen/ARM64/2013-01-23-sext-crash.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

38 lines
961 B
LLVM

; RUN: llc < %s -march=arm64
; Make sure we are not crashing on this test.
define void @autogen_SD12881() {
BB:
%B17 = ashr <4 x i32> zeroinitializer, zeroinitializer
br label %CF
CF: ; preds = %CF83, %CF, %BB
br i1 undef, label %CF, label %CF83
CF83: ; preds = %CF
%FC70 = sitofp <4 x i32> %B17 to <4 x double>
br label %CF
}
define void @autogen_SD12881_2() {
BB:
%B17 = ashr <4 x i32> zeroinitializer, zeroinitializer
br label %CF
CF: ; preds = %CF83, %CF, %BB
br i1 undef, label %CF, label %CF83
CF83: ; preds = %CF
%FC70 = uitofp <4 x i32> %B17 to <4 x double>
br label %CF
}
define void @_Z12my_example2bv() nounwind noinline ssp {
entry:
%0 = fptosi <2 x double> undef to <2 x i32>
store <2 x i32> %0, <2 x i32>* undef, align 8
ret void
}