mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
91 lines
2.2 KiB
LLVM
91 lines
2.2 KiB
LLVM
; RUN: llc < %s -march=arm64 | FileCheck %s
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; rdar://9296808
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; rdar://9349137
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define i128 @t1(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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; CHECK: umulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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%tmp1 = zext i64 %a to i128
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%tmp2 = zext i64 %b to i128
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%tmp3 = mul i128 %tmp1, %tmp2
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ret i128 %tmp3
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}
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define i128 @t2(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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; CHECK: smulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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%tmp1 = sext i64 %a to i128
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%tmp2 = sext i64 %b to i128
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%tmp3 = mul i128 %tmp1, %tmp2
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ret i128 %tmp3
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}
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define i64 @t3(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: umull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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ret i64 %tmp3
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}
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define i64 @t4(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK-LABEL: t4:
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; CHECK: smull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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%tmp1 = sext i32 %a to i64
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%tmp2 = sext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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ret i64 %tmp3
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}
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define i64 @t5(i32 %a, i32 %b, i64 %c) nounwind {
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entry:
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; CHECK-LABEL: t5:
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; CHECK: umaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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%tmp4 = add i64 %c, %tmp3
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ret i64 %tmp4
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}
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define i64 @t6(i32 %a, i32 %b, i64 %c) nounwind {
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entry:
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; CHECK-LABEL: t6:
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; CHECK: smsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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%tmp1 = sext i32 %a to i64
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%tmp2 = sext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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%tmp4 = sub i64 %c, %tmp3
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ret i64 %tmp4
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}
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define i64 @t7(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK-LABEL: t7:
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; CHECK: umnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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%tmp4 = sub i64 0, %tmp3
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ret i64 %tmp4
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}
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define i64 @t8(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK-LABEL: t8:
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; CHECK: smnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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%tmp1 = sext i32 %a to i64
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%tmp2 = sext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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%tmp4 = sub i64 0, %tmp3
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ret i64 %tmp4
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}
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