mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 01:30:19 +00:00
86a791284a
The "half vectors" are now widened to full size by the legalizer. The only exception is in parameter passing, where half vectors are expanded. This causes changes to some dejagnu tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111360 91177308-0d34-0410-b5e6-96231b3b80d8
430 lines
19 KiB
TableGen
430 lines
19 KiB
TableGen
//===- SPURegisterInfo.td - The Cell SPU Register File -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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class SPUReg<string n> : Register<n> {
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let Namespace = "SPU";
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}
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// The SPU's register are all 128-bits wide, which makes specifying the
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// registers relatively easy, if relatively mundane:
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class SPUVecReg<bits<7> num, string n> : SPUReg<n> {
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field bits<7> Num = num;
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}
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def R0 : SPUVecReg<0, "$lr">, DwarfRegNum<[0]>;
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def R1 : SPUVecReg<1, "$sp">, DwarfRegNum<[1]>;
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def R2 : SPUVecReg<2, "$2">, DwarfRegNum<[2]>;
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def R3 : SPUVecReg<3, "$3">, DwarfRegNum<[3]>;
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def R4 : SPUVecReg<4, "$4">, DwarfRegNum<[4]>;
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def R5 : SPUVecReg<5, "$5">, DwarfRegNum<[5]>;
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def R6 : SPUVecReg<6, "$6">, DwarfRegNum<[6]>;
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def R7 : SPUVecReg<7, "$7">, DwarfRegNum<[7]>;
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def R8 : SPUVecReg<8, "$8">, DwarfRegNum<[8]>;
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def R9 : SPUVecReg<9, "$9">, DwarfRegNum<[9]>;
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def R10 : SPUVecReg<10, "$10">, DwarfRegNum<[10]>;
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def R11 : SPUVecReg<11, "$11">, DwarfRegNum<[11]>;
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def R12 : SPUVecReg<12, "$12">, DwarfRegNum<[12]>;
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def R13 : SPUVecReg<13, "$13">, DwarfRegNum<[13]>;
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def R14 : SPUVecReg<14, "$14">, DwarfRegNum<[14]>;
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def R15 : SPUVecReg<15, "$15">, DwarfRegNum<[15]>;
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def R16 : SPUVecReg<16, "$16">, DwarfRegNum<[16]>;
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def R17 : SPUVecReg<17, "$17">, DwarfRegNum<[17]>;
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def R18 : SPUVecReg<18, "$18">, DwarfRegNum<[18]>;
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def R19 : SPUVecReg<19, "$19">, DwarfRegNum<[19]>;
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def R20 : SPUVecReg<20, "$20">, DwarfRegNum<[20]>;
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def R21 : SPUVecReg<21, "$21">, DwarfRegNum<[21]>;
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def R22 : SPUVecReg<22, "$22">, DwarfRegNum<[22]>;
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def R23 : SPUVecReg<23, "$23">, DwarfRegNum<[23]>;
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def R24 : SPUVecReg<24, "$24">, DwarfRegNum<[24]>;
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def R25 : SPUVecReg<25, "$25">, DwarfRegNum<[25]>;
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def R26 : SPUVecReg<26, "$26">, DwarfRegNum<[26]>;
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def R27 : SPUVecReg<27, "$27">, DwarfRegNum<[27]>;
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def R28 : SPUVecReg<28, "$28">, DwarfRegNum<[28]>;
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def R29 : SPUVecReg<29, "$29">, DwarfRegNum<[29]>;
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def R30 : SPUVecReg<30, "$30">, DwarfRegNum<[30]>;
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def R31 : SPUVecReg<31, "$31">, DwarfRegNum<[31]>;
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def R32 : SPUVecReg<32, "$32">, DwarfRegNum<[32]>;
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def R33 : SPUVecReg<33, "$33">, DwarfRegNum<[33]>;
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def R34 : SPUVecReg<34, "$34">, DwarfRegNum<[34]>;
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def R35 : SPUVecReg<35, "$35">, DwarfRegNum<[35]>;
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def R36 : SPUVecReg<36, "$36">, DwarfRegNum<[36]>;
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def R37 : SPUVecReg<37, "$37">, DwarfRegNum<[37]>;
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def R38 : SPUVecReg<38, "$38">, DwarfRegNum<[38]>;
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def R39 : SPUVecReg<39, "$39">, DwarfRegNum<[39]>;
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def R40 : SPUVecReg<40, "$40">, DwarfRegNum<[40]>;
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def R41 : SPUVecReg<41, "$41">, DwarfRegNum<[41]>;
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def R42 : SPUVecReg<42, "$42">, DwarfRegNum<[42]>;
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def R43 : SPUVecReg<43, "$43">, DwarfRegNum<[43]>;
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def R44 : SPUVecReg<44, "$44">, DwarfRegNum<[44]>;
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def R45 : SPUVecReg<45, "$45">, DwarfRegNum<[45]>;
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def R46 : SPUVecReg<46, "$46">, DwarfRegNum<[46]>;
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def R47 : SPUVecReg<47, "$47">, DwarfRegNum<[47]>;
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def R48 : SPUVecReg<48, "$48">, DwarfRegNum<[48]>;
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def R49 : SPUVecReg<49, "$49">, DwarfRegNum<[49]>;
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def R50 : SPUVecReg<50, "$50">, DwarfRegNum<[50]>;
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def R51 : SPUVecReg<51, "$51">, DwarfRegNum<[51]>;
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def R52 : SPUVecReg<52, "$52">, DwarfRegNum<[52]>;
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def R53 : SPUVecReg<53, "$53">, DwarfRegNum<[53]>;
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def R54 : SPUVecReg<54, "$54">, DwarfRegNum<[54]>;
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def R55 : SPUVecReg<55, "$55">, DwarfRegNum<[55]>;
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def R56 : SPUVecReg<56, "$56">, DwarfRegNum<[56]>;
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def R57 : SPUVecReg<57, "$57">, DwarfRegNum<[57]>;
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def R58 : SPUVecReg<58, "$58">, DwarfRegNum<[58]>;
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def R59 : SPUVecReg<59, "$59">, DwarfRegNum<[59]>;
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def R60 : SPUVecReg<60, "$60">, DwarfRegNum<[60]>;
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def R61 : SPUVecReg<61, "$61">, DwarfRegNum<[61]>;
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def R62 : SPUVecReg<62, "$62">, DwarfRegNum<[62]>;
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def R63 : SPUVecReg<63, "$63">, DwarfRegNum<[63]>;
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def R64 : SPUVecReg<64, "$64">, DwarfRegNum<[64]>;
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def R65 : SPUVecReg<65, "$65">, DwarfRegNum<[65]>;
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def R66 : SPUVecReg<66, "$66">, DwarfRegNum<[66]>;
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def R67 : SPUVecReg<67, "$67">, DwarfRegNum<[67]>;
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def R68 : SPUVecReg<68, "$68">, DwarfRegNum<[68]>;
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def R69 : SPUVecReg<69, "$69">, DwarfRegNum<[69]>;
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def R70 : SPUVecReg<70, "$70">, DwarfRegNum<[70]>;
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def R71 : SPUVecReg<71, "$71">, DwarfRegNum<[71]>;
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def R72 : SPUVecReg<72, "$72">, DwarfRegNum<[72]>;
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def R73 : SPUVecReg<73, "$73">, DwarfRegNum<[73]>;
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def R74 : SPUVecReg<74, "$74">, DwarfRegNum<[74]>;
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def R75 : SPUVecReg<75, "$75">, DwarfRegNum<[75]>;
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def R76 : SPUVecReg<76, "$76">, DwarfRegNum<[76]>;
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def R77 : SPUVecReg<77, "$77">, DwarfRegNum<[77]>;
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def R78 : SPUVecReg<78, "$78">, DwarfRegNum<[78]>;
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def R79 : SPUVecReg<79, "$79">, DwarfRegNum<[79]>;
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def R80 : SPUVecReg<80, "$80">, DwarfRegNum<[80]>;
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def R81 : SPUVecReg<81, "$81">, DwarfRegNum<[81]>;
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def R82 : SPUVecReg<82, "$82">, DwarfRegNum<[82]>;
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def R83 : SPUVecReg<83, "$83">, DwarfRegNum<[83]>;
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def R84 : SPUVecReg<84, "$84">, DwarfRegNum<[84]>;
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def R85 : SPUVecReg<85, "$85">, DwarfRegNum<[85]>;
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def R86 : SPUVecReg<86, "$86">, DwarfRegNum<[86]>;
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def R87 : SPUVecReg<87, "$87">, DwarfRegNum<[87]>;
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def R88 : SPUVecReg<88, "$88">, DwarfRegNum<[88]>;
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def R89 : SPUVecReg<89, "$89">, DwarfRegNum<[89]>;
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def R90 : SPUVecReg<90, "$90">, DwarfRegNum<[90]>;
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def R91 : SPUVecReg<91, "$91">, DwarfRegNum<[91]>;
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def R92 : SPUVecReg<92, "$92">, DwarfRegNum<[92]>;
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def R93 : SPUVecReg<93, "$93">, DwarfRegNum<[93]>;
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def R94 : SPUVecReg<94, "$94">, DwarfRegNum<[94]>;
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def R95 : SPUVecReg<95, "$95">, DwarfRegNum<[95]>;
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def R96 : SPUVecReg<96, "$96">, DwarfRegNum<[96]>;
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def R97 : SPUVecReg<97, "$97">, DwarfRegNum<[97]>;
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def R98 : SPUVecReg<98, "$98">, DwarfRegNum<[98]>;
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def R99 : SPUVecReg<99, "$99">, DwarfRegNum<[99]>;
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def R100 : SPUVecReg<100, "$100">, DwarfRegNum<[100]>;
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def R101 : SPUVecReg<101, "$101">, DwarfRegNum<[101]>;
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def R102 : SPUVecReg<102, "$102">, DwarfRegNum<[102]>;
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def R103 : SPUVecReg<103, "$103">, DwarfRegNum<[103]>;
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def R104 : SPUVecReg<104, "$104">, DwarfRegNum<[104]>;
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def R105 : SPUVecReg<105, "$105">, DwarfRegNum<[105]>;
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def R106 : SPUVecReg<106, "$106">, DwarfRegNum<[106]>;
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def R107 : SPUVecReg<107, "$107">, DwarfRegNum<[107]>;
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def R108 : SPUVecReg<108, "$108">, DwarfRegNum<[108]>;
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def R109 : SPUVecReg<109, "$109">, DwarfRegNum<[109]>;
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def R110 : SPUVecReg<110, "$110">, DwarfRegNum<[110]>;
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def R111 : SPUVecReg<111, "$111">, DwarfRegNum<[111]>;
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def R112 : SPUVecReg<112, "$112">, DwarfRegNum<[112]>;
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def R113 : SPUVecReg<113, "$113">, DwarfRegNum<[113]>;
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def R114 : SPUVecReg<114, "$114">, DwarfRegNum<[114]>;
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def R115 : SPUVecReg<115, "$115">, DwarfRegNum<[115]>;
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def R116 : SPUVecReg<116, "$116">, DwarfRegNum<[116]>;
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def R117 : SPUVecReg<117, "$117">, DwarfRegNum<[117]>;
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def R118 : SPUVecReg<118, "$118">, DwarfRegNum<[118]>;
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def R119 : SPUVecReg<119, "$119">, DwarfRegNum<[119]>;
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def R120 : SPUVecReg<120, "$120">, DwarfRegNum<[120]>;
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def R121 : SPUVecReg<121, "$121">, DwarfRegNum<[121]>;
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def R122 : SPUVecReg<122, "$122">, DwarfRegNum<[122]>;
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def R123 : SPUVecReg<123, "$123">, DwarfRegNum<[123]>;
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def R124 : SPUVecReg<124, "$124">, DwarfRegNum<[124]>;
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def R125 : SPUVecReg<125, "$125">, DwarfRegNum<[125]>;
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def R126 : SPUVecReg<126, "$126">, DwarfRegNum<[126]>;
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def R127 : SPUVecReg<127, "$127">, DwarfRegNum<[127]>;
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/* Need floating point status register here: */
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/* def FPCSR : ... */
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// The SPU's registers as 128-bit wide entities, and can function as general
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// purpose registers, where the operands are in the "preferred slot":
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def GPRC : RegisterClass<"SPU", [i128], 128,
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[
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/* volatile register */
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R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
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R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
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R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
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R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
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R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
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R77, R78, R79,
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/* non-volatile register: take hint from PPC and allocate in reverse order */
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R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
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R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
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R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
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R86, R85, R84, R83, R82, R81, R80,
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/* environment ptr, SP, LR */
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R2, R1, R0 ]>
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{
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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GPRCClass::iterator
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GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
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return begin();
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}
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GPRCClass::iterator
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GPRCClass::allocation_order_end(const MachineFunction &MF) const {
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return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
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}
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}];
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}
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// The SPU's registers as 64-bit wide (double word integer) "preferred slot":
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def R64C : RegisterClass<"SPU", [i64], 128,
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[
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/* volatile register */
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R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
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R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
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R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
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R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
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R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
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R77, R78, R79,
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/* non-volatile register: take hint from PPC and allocate in reverse order */
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R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
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R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
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R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
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R86, R85, R84, R83, R82, R81, R80,
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/* environment ptr, SP, LR */
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R2, R1, R0 ]>
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{
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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R64CClass::iterator
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R64CClass::allocation_order_begin(const MachineFunction &MF) const {
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return begin();
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}
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R64CClass::iterator
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R64CClass::allocation_order_end(const MachineFunction &MF) const {
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return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
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}
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}];
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}
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// The SPU's registers as 64-bit wide (double word) FP "preferred slot":
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def R64FP : RegisterClass<"SPU", [f64], 128,
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[
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/* volatile register */
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R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
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R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
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R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
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R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
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R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
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R77, R78, R79,
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/* non-volatile register: take hint from PPC and allocate in reverse order */
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R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
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R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
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R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
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R86, R85, R84, R83, R82, R81, R80,
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/* environment ptr, SP, LR */
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R2, R1, R0 ]>
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{
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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R64FPClass::iterator
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R64FPClass::allocation_order_begin(const MachineFunction &MF) const {
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return begin();
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}
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R64FPClass::iterator
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R64FPClass::allocation_order_end(const MachineFunction &MF) const {
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return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
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}
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}];
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}
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// The SPU's registers as 32-bit wide (word) "preferred slot":
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def R32C : RegisterClass<"SPU", [i32], 128,
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[
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/* volatile register */
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R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
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R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
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R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
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R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
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R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
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R77, R78, R79,
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/* non-volatile register: take hint from PPC and allocate in reverse order */
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R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
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R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
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R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
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R86, R85, R84, R83, R82, R81, R80,
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/* environment ptr, SP, LR */
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R2, R1, R0 ]>
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{
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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R32CClass::iterator
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R32CClass::allocation_order_begin(const MachineFunction &MF) const {
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return begin();
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}
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R32CClass::iterator
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R32CClass::allocation_order_end(const MachineFunction &MF) const {
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return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
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}
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}];
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}
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// The SPU's registers as single precision floating point "preferred slot":
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def R32FP : RegisterClass<"SPU", [f32], 128,
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[
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/* volatile register */
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R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
|
|
R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
|
|
R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
|
|
R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
|
|
R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
|
|
R77, R78, R79,
|
|
/* non-volatile register: take hint from PPC and allocate in reverse order */
|
|
R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
|
|
R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
|
|
R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
|
|
R86, R85, R84, R83, R82, R81, R80,
|
|
/* environment ptr, SP, LR */
|
|
R2, R1, R0 ]>
|
|
{
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
R32FPClass::iterator
|
|
R32FPClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
return begin();
|
|
}
|
|
R32FPClass::iterator
|
|
R32FPClass::allocation_order_end(const MachineFunction &MF) const {
|
|
return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
|
|
}
|
|
}];
|
|
}
|
|
|
|
// The SPU's registers as 16-bit wide (halfword) "preferred slot":
|
|
def R16C : RegisterClass<"SPU", [i16], 128,
|
|
[
|
|
/* volatile register */
|
|
R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
|
|
R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
|
|
R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
|
|
R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
|
|
R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
|
|
R77, R78, R79,
|
|
/* non-volatile register: take hint from PPC and allocate in reverse order */
|
|
R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
|
|
R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
|
|
R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
|
|
R86, R85, R84, R83, R82, R81, R80,
|
|
/* environment ptr, SP, LR */
|
|
R2, R1, R0 ]>
|
|
{
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
R16CClass::iterator
|
|
R16CClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
return begin();
|
|
}
|
|
R16CClass::iterator
|
|
R16CClass::allocation_order_end(const MachineFunction &MF) const {
|
|
return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
|
|
}
|
|
}];
|
|
}
|
|
|
|
// The SPU's registers as 8-bit wide (byte) "preferred slot":
|
|
def R8C : RegisterClass<"SPU", [i8], 128,
|
|
[
|
|
/* volatile register */
|
|
R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
|
|
R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
|
|
R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
|
|
R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
|
|
R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
|
|
R77, R78, R79,
|
|
/* non-volatile register: take hint from PPC and allocate in reverse order */
|
|
R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
|
|
R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
|
|
R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
|
|
R86, R85, R84, R83, R82, R81, R80,
|
|
/* environment ptr, SP, LR */
|
|
R2, R1, R0 ]>
|
|
{
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
R8CClass::iterator
|
|
R8CClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
return begin();
|
|
}
|
|
R8CClass::iterator
|
|
R8CClass::allocation_order_end(const MachineFunction &MF) const {
|
|
return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
|
|
}
|
|
}];
|
|
}
|
|
|
|
// The SPU's registers as vector registers:
|
|
def VECREG : RegisterClass<"SPU",
|
|
[v16i8,v8i16,v4i32,v4f32,v2i64,v2f64],
|
|
128,
|
|
[
|
|
/* volatile register */
|
|
R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
|
|
R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
|
|
R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
|
|
R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
|
|
R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
|
|
R77, R78, R79,
|
|
/* non-volatile register: take hint from PPC and allocate in reverse order */
|
|
R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
|
|
R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
|
|
R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
|
|
R86, R85, R84, R83, R82, R81, R80,
|
|
/* environment ptr, SP, LR */
|
|
R2, R1, R0 ]>
|
|
{
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
VECREGClass::iterator
|
|
VECREGClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
return begin();
|
|
}
|
|
VECREGClass::iterator
|
|
VECREGClass::allocation_order_end(const MachineFunction &MF) const {
|
|
return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
|
|
}
|
|
}];
|
|
}
|