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than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227102 91177308-0d34-0410-b5e6-96231b3b80d8
89 lines
2.9 KiB
C++
89 lines
2.9 KiB
C++
//===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsABIInfo.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/MCTargetOptions.h"
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using namespace llvm;
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namespace {
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static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
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static const MCPhysReg Mips64IntRegs[8] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
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Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
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}
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const ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
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if (IsO32())
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return makeArrayRef(O32IntRegs);
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if (IsN32() || IsN64())
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return makeArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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}
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const ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
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if (IsO32())
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return makeArrayRef(O32IntRegs);
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if (IsN32() || IsN64())
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return makeArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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}
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unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
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if (IsO32())
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return CC != CallingConv::Fast ? 16 : 0;
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if (IsN32() || IsN64() || IsEABI())
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return 0;
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llvm_unreachable("Unhandled ABI");
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}
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MipsABIInfo MipsABIInfo::computeTargetABI(Triple TT, StringRef CPU,
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const MCTargetOptions &Options) {
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if (Options.getABIName().startswith("o32"))
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return MipsABIInfo::O32();
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else if (Options.getABIName().startswith("n32"))
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return MipsABIInfo::N32();
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else if (Options.getABIName().startswith("n64"))
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return MipsABIInfo::N64();
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else if (Options.getABIName().startswith("eabi"))
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return MipsABIInfo::EABI();
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else if (!Options.getABIName().empty())
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llvm_unreachable("Unknown ABI option for MIPS");
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// FIXME: This shares code with the selectMipsCPU routine that's
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// used and not shared in a couple of other places. This needs unifying
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// at some level.
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if (CPU.empty() || CPU == "generic") {
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if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
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CPU = "mips32";
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else
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CPU = "mips64";
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}
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return StringSwitch<MipsABIInfo>(CPU)
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.Case("mips1", MipsABIInfo::O32())
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.Case("mips2", MipsABIInfo::O32())
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.Case("mips32", MipsABIInfo::O32())
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.Case("mips32r2", MipsABIInfo::O32())
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.Case("mips32r6", MipsABIInfo::O32())
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.Case("mips16", MipsABIInfo::O32())
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.Case("mips3", MipsABIInfo::N64())
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.Case("mips4", MipsABIInfo::N64())
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.Case("mips5", MipsABIInfo::N64())
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.Case("mips64", MipsABIInfo::N64())
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.Case("mips64r2", MipsABIInfo::N64())
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.Case("mips64r6", MipsABIInfo::N64())
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.Case("octeon", MipsABIInfo::N64())
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.Default(MipsABIInfo::Unknown());
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}
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