llvm-6502/test/CodeGen/SystemZ/fp-neg-01.ll
Ulrich Weigand cf0fa9b9dd [SystemZ] Add CodeGen support for scalar f64 ops in vector registers
The z13 vector facility includes some instructions that operate only on the
high f64 in a v2f64, effectively extending the FP register set from 16
to 32 registers.  It's still better to use the old instructions if the
operands happen to fit though, since the older instructions have a shorter
encoding.

Based on a patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236524 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05 19:28:34 +00:00

40 lines
1.0 KiB
LLVM

; Test floating-point negation.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
; Test f32.
define float @f1(float %f) {
; CHECK-LABEL: f1:
; CHECK: lcebr %f0, %f0
; CHECK: br %r14
%res = fsub float -0.0, %f
ret float %res
}
; Test f64.
define double @f2(double %f) {
; CHECK-LABEL: f2:
; CHECK: lcdbr %f0, %f0
; CHECK: br %r14
%res = fsub double -0.0, %f
ret double %res
}
; Test f128. With the loads and stores, a pure negation would probably
; be better implemented using an XI on the upper byte. Do some extra
; processing so that using FPRs is unequivocally better.
define void @f3(fp128 *%ptr, fp128 *%ptr2) {
; CHECK-LABEL: f3:
; CHECK: lcxbr
; CHECK: dxbr
; CHECK: br %r14
%orig = load fp128 , fp128 *%ptr
%negzero = fpext float -0.0 to fp128
%neg = fsub fp128 0xL00000000000000008000000000000000, %orig
%op2 = load fp128 , fp128 *%ptr2
%res = fdiv fp128 %neg, %op2
store fp128 %res, fp128 *%ptr
ret void
}