mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
115 lines
2.5 KiB
LLVM
115 lines
2.5 KiB
LLVM
; Test 32-bit logical shifts right.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check the low end of the SRL range.
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define i32 @f1(i32 %a) {
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; CHECK-LABEL: f1:
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; CHECK: srl %r2, 1
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; CHECK: br %r14
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%shift = lshr i32 %a, 1
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ret i32 %shift
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}
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; Check the high end of the defined SRL range.
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define i32 @f2(i32 %a) {
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; CHECK-LABEL: f2:
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; CHECK: srl %r2, 31
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; CHECK: br %r14
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%shift = lshr i32 %a, 31
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ret i32 %shift
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}
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; We don't generate shifts by out-of-range values.
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define i32 @f3(i32 %a) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: srl %r2, 32
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; CHECK: br %r14
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%shift = lshr i32 %a, 32
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ret i32 %shift
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}
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; Make sure that we don't generate negative shift amounts.
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define i32 @f4(i32 %a, i32 %amt) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: srl %r2, -1{{.*}}
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; CHECK: br %r14
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%sub = sub i32 %amt, 1
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%shift = lshr i32 %a, %sub
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ret i32 %shift
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}
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; Check variable shifts.
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define i32 @f5(i32 %a, i32 %amt) {
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; CHECK-LABEL: f5:
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; CHECK: srl %r2, 0(%r3)
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; CHECK: br %r14
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%shift = lshr i32 %a, %amt
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ret i32 %shift
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}
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; Check shift amounts that have a constant term.
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define i32 @f6(i32 %a, i32 %amt) {
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; CHECK-LABEL: f6:
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; CHECK: srl %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i32 %amt, 10
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%shift = lshr i32 %a, %add
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ret i32 %shift
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}
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; ...and again with a truncated 64-bit shift amount.
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define i32 @f7(i32 %a, i64 %amt) {
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; CHECK-LABEL: f7:
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; CHECK: srl %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i64 %amt, 10
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%trunc = trunc i64 %add to i32
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%shift = lshr i32 %a, %trunc
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ret i32 %shift
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}
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; Check shift amounts that have the largest in-range constant term. We could
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; mask the amount instead.
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define i32 @f8(i32 %a, i32 %amt) {
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; CHECK-LABEL: f8:
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; CHECK: srl %r2, 4095(%r3)
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; CHECK: br %r14
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%add = add i32 %amt, 4095
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%shift = lshr i32 %a, %add
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ret i32 %shift
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}
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; Check the next value up. Again, we could mask the amount instead.
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define i32 @f9(i32 %a, i32 %amt) {
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; CHECK-LABEL: f9:
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; CHECK: ahi %r3, 4096
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; CHECK: srl %r2, 0(%r3)
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; CHECK: br %r14
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%add = add i32 %amt, 4096
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%shift = lshr i32 %a, %add
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ret i32 %shift
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}
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; Check that we don't try to generate "indexed" shifts.
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define i32 @f10(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: f10:
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; CHECK: ar {{%r3, %r4|%r4, %r3}}
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; CHECK: srl %r2, 0({{%r[34]}})
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; CHECK: br %r14
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%add = add i32 %b, %c
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%shift = lshr i32 %a, %add
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ret i32 %shift
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}
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; Check that the shift amount uses an address register. It cannot be in %r0.
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define i32 @f11(i32 %a, i32 *%ptr) {
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; CHECK-LABEL: f11:
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; CHECK: l %r1, 0(%r3)
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; CHECK: srl %r2, 0(%r1)
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; CHECK: br %r14
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%amt = load i32 , i32 *%ptr
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%shift = lshr i32 %a, %amt
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ret i32 %shift
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}
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