mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
1.2 KiB
LLVM
50 lines
1.2 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon -pre-RA-sched=source -disable-post-ra %s -o - \
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; RUN: | FileCheck %s
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define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vrecpe.f32
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;CHECK: vmovn.i32
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;CHECK: vrecpe.f32
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;CHECK: vmovn.i32
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;CHECK: vmovn.i16
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = sdiv <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vrecpe.f32
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;CHECK: vrecps.f32
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;CHECK: vmovn.i32
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;CHECK: vrecpe.f32
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;CHECK: vrecps.f32
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;CHECK: vmovn.i32
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;CHECK: vqmovun.s16
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = udiv <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vrecpe.f32
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;CHECK: vrecps.f32
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;CHECK: vmovn.i32
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = sdiv <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <4 x i16> @udivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vrecpe.f32
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;CHECK: vrecps.f32
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;CHECK: vrecps.f32
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;CHECK: vmovn.i32
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = udiv <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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