Nick Lewycky d8d1584c13 The sign of an srem instruction is the sign of its dividend (the first ... argument), regardless of the divisor. Teach instcombine about this and fix test7 in PR9343! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126635 91177308-0d34-0410-b5e6-96231b3b80d8		2011-02-28 06:20:05 +00:00
..
CMakeLists.txt	Removed a bunch of unnecessary target_link_libraries.	2010-09-28 22:39:14 +00:00
InstCombine.h	refactor some code out into a helper method.	2011-02-13 07:43:07 +00:00
InstCombineAddSub.cpp	add is always integer, thanks to Frits for noticing this.	2011-02-17 20:55:29 +00:00
InstCombineAndOrXor.cpp	Move "A | ~(A & ?) -> -1" from InstCombine to InstructionSimplify.	2011-02-20 15:20:01 +00:00
InstCombineCalls.cpp	change instcombine to not turn a call to non-varargs bitcast of	2011-02-24 05:10:56 +00:00
InstCombineCasts.cpp	convert ConstantVector::get to use ArrayRef.	2011-02-15 00:14:00 +00:00
InstCombineCompares.cpp	The sign of an srem instruction is the sign of its dividend (the first	2011-02-28 06:20:05 +00:00
InstCombineLoadStoreAlloca.cpp	Spelling fix: consequtive -> consecutive.	2011-02-15 09:23:02 +00:00
InstCombineMulDivRem.cpp	Enhance a bunch of transformations in instcombine to start generating	2011-02-10 05:36:31 +00:00
InstCombinePHI.cpp	have instcombine preserve nsw/nuw/exact when sinking	2011-02-17 23:01:49 +00:00
InstCombineSelect.cpp	Fold select + select where both selects are on the same condition.	2011-01-28 03:28:10 +00:00
InstCombineShifts.cpp	Enhance a bunch of transformations in instcombine to start generating	2011-02-10 05:36:31 +00:00
InstCombineSimplifyDemanded.cpp	teach SimplifyDemandedBits that exact shifts demand the bits they	2011-02-10 05:09:34 +00:00
InstCombineVectorOps.cpp	PR9218: SimplifyDemandedVectorElts can return a non-null value that is not	2011-02-19 22:42:40 +00:00
InstCombineWorklist.h
InstructionCombining.cpp	Do not forget DebugLoc!	2011-02-15 02:02:30 +00:00
Makefile