mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ac34a00fe0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56117 91177308-0d34-0410-b5e6-96231b3b80d8
1095 lines
34 KiB
C++
1095 lines
34 KiB
C++
//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86-specific support for the FastISel class. Much
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// of the target-specific code is generated by tablegen in the file
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// X86GenFastISel.inc, which is #included here.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrBuilder.h"
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#include "X86ISelLowering.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/CallingConv.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Instructions.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CallSite.h"
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using namespace llvm;
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class X86FastISel : public FastISel {
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/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const X86Subtarget *Subtarget;
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/// StackPtr - Register used as the stack pointer.
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///
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unsigned StackPtr;
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/// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
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/// floating point ops.
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/// When SSE is available, use it for f32 operations.
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/// When SSE2 is available, use it for f64 operations.
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bool X86ScalarSSEf64;
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bool X86ScalarSSEf32;
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public:
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explicit X86FastISel(MachineFunction &mf,
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DenseMap<const Value *, unsigned> &vm,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
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DenseMap<const AllocaInst *, int> &am)
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: FastISel(mf, vm, bm, am) {
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
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X86ScalarSSEf64 = Subtarget->hasSSE2();
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X86ScalarSSEf32 = Subtarget->hasSSE1();
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}
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virtual bool TargetSelectInstruction(Instruction *I);
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#include "X86GenFastISel.inc"
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private:
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bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
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bool X86FastEmitStore(MVT VT, unsigned Val,
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const X86AddressMode &AM);
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bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
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unsigned &ResultReg);
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bool X86SelectConstAddr(Value *V, unsigned &Op0,
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bool isCall = false, bool inReg = false);
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bool X86SelectAddress(Value *V, X86AddressMode &AM);
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bool X86SelectLoad(Instruction *I);
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bool X86SelectStore(Instruction *I);
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bool X86SelectCmp(Instruction *I);
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bool X86SelectZExt(Instruction *I);
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bool X86SelectBranch(Instruction *I);
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bool X86SelectShift(Instruction *I);
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bool X86SelectSelect(Instruction *I);
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bool X86SelectTrunc(Instruction *I);
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bool X86SelectFPExt(Instruction *I);
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bool X86SelectFPTrunc(Instruction *I);
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bool X86SelectCall(Instruction *I);
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CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
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unsigned TargetMaterializeConstant(Constant *C);
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unsigned TargetMaterializeAlloca(AllocaInst *C);
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/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
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/// computed in an SSE register, not on the X87 floating point stack.
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bool isScalarFPTypeInSSEReg(MVT VT) const {
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return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
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(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
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}
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};
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static bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT,
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bool AllowI1 = false) {
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VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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if (VT == MVT::iPTR)
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// Use pointer type.
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VT = TLI.getPointerTy();
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// We only handle legal types. For example, on x86-32 the instruction
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// selector contains all of the 64-bit instructions from x86-64,
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// under the assumption that i64 won't be used if the target doesn't
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// support it.
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return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
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}
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#include "X86GenCallingConv.inc"
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/// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
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/// convention.
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CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) {
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if (Subtarget->is64Bit()) {
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if (Subtarget->isTargetWin64())
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return CC_X86_Win64_C;
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else if (CC == CallingConv::Fast && isTaillCall)
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return CC_X86_64_TailCall;
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else
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return CC_X86_64_C;
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}
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if (CC == CallingConv::X86_FastCall)
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return CC_X86_32_FastCall;
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else if (CC == CallingConv::Fast && isTaillCall)
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return CC_X86_32_TailCall;
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else if (CC == CallingConv::Fast)
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return CC_X86_32_FastCC;
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else
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return CC_X86_32_C;
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}
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/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
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/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
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/// Return true and the result register by reference if it is possible.
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bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM,
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unsigned &ResultReg) {
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// Get opcode and regclass of the output for the given load instruction.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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switch (VT.getSimpleVT()) {
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default: return false;
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case MVT::i8:
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Opc = X86::MOV8rm;
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RC = X86::GR8RegisterClass;
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break;
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case MVT::i16:
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Opc = X86::MOV16rm;
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RC = X86::GR16RegisterClass;
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break;
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case MVT::i32:
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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break;
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case MVT::i64:
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// Must be in x86-64 mode.
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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break;
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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Opc = X86::MOVSSrm;
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RC = X86::FR32RegisterClass;
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} else {
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Opc = X86::LD_Fp32m;
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RC = X86::RFP32RegisterClass;
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}
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break;
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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Opc = X86::MOVSDrm;
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RC = X86::FR64RegisterClass;
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} else {
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Opc = X86::LD_Fp64m;
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RC = X86::RFP64RegisterClass;
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}
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break;
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case MVT::f80:
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Opc = X86::LD_Fp80m;
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RC = X86::RFP80RegisterClass;
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break;
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}
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ResultReg = createResultReg(RC);
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addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
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return true;
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}
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/// X86FastEmitStore - Emit a machine instruction to store a value Val of
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/// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
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/// and a displacement offset, or a GlobalAddress,
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/// i.e. V. Return true if it is possible.
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bool
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X86FastISel::X86FastEmitStore(MVT VT, unsigned Val,
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const X86AddressMode &AM) {
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// Get opcode and regclass of the output for the given store instruction.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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switch (VT.getSimpleVT()) {
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default: return false;
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case MVT::i8:
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Opc = X86::MOV8mr;
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RC = X86::GR8RegisterClass;
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break;
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case MVT::i16:
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Opc = X86::MOV16mr;
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RC = X86::GR16RegisterClass;
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break;
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case MVT::i32:
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Opc = X86::MOV32mr;
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RC = X86::GR32RegisterClass;
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break;
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case MVT::i64:
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// Must be in x86-64 mode.
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Opc = X86::MOV64mr;
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RC = X86::GR64RegisterClass;
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break;
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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Opc = X86::MOVSSmr;
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RC = X86::FR32RegisterClass;
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} else {
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Opc = X86::ST_Fp32m;
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RC = X86::RFP32RegisterClass;
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}
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break;
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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Opc = X86::MOVSDmr;
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RC = X86::FR64RegisterClass;
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} else {
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Opc = X86::ST_Fp64m;
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RC = X86::RFP64RegisterClass;
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}
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break;
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case MVT::f80:
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Opc = X86::ST_FP80m;
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RC = X86::RFP80RegisterClass;
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break;
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}
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addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Val);
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return true;
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}
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/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
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/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
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/// ISD::SIGN_EXTEND).
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bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
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unsigned Src, MVT SrcVT,
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unsigned &ResultReg) {
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unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
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if (RR != 0) {
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ResultReg = RR;
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return true;
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} else
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return false;
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}
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/// X86SelectConstAddr - Select and emit code to materialize constant address.
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///
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bool X86FastISel::X86SelectConstAddr(Value *V, unsigned &Op0,
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bool isCall, bool inReg) {
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// FIXME: Only GlobalAddress for now.
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GlobalValue *GV = dyn_cast<GlobalValue>(V);
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if (!GV)
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return false;
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if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
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// Issue load from stub if necessary.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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if (TLI.getPointerTy() == MVT::i32) {
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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} else {
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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}
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Op0 = createResultReg(RC);
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X86AddressMode AM;
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AM.GV = GV;
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addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
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// Prevent loading GV stub multiple times in same MBB.
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LocalValueMap[V] = Op0;
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} else if (inReg) {
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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if (TLI.getPointerTy() == MVT::i32) {
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Opc = X86::LEA32r;
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RC = X86::GR32RegisterClass;
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} else {
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Opc = X86::LEA64r;
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RC = X86::GR64RegisterClass;
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}
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Op0 = createResultReg(RC);
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X86AddressMode AM;
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AM.GV = GV;
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addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
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// Prevent materializing GV address multiple times in same MBB.
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LocalValueMap[V] = Op0;
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}
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return true;
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}
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/// X86SelectAddress - Attempt to fill in an address from the given value.
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///
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bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) {
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// Look past bitcasts.
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if (const BitCastInst *BC = dyn_cast<BitCastInst>(V))
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return X86SelectAddress(BC->getOperand(0), AM);
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if (const AllocaInst *A = dyn_cast<AllocaInst>(V)) {
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DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
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if (SI == StaticAllocaMap.end())
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return false;
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AM.BaseType = X86AddressMode::FrameIndexBase;
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AM.Base.FrameIndex = SI->second;
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} else if (unsigned Ptr = lookUpRegForValue(V)) {
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AM.Base.Reg = Ptr;
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} else {
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// Handle constant address.
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// FIXME: If load type is something we can't handle, this can result in
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// a dead stub load instruction.
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if (isa<Constant>(V) && X86SelectConstAddr(V, AM.Base.Reg)) {
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if (AM.Base.Reg == 0)
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AM.GV = cast<GlobalValue>(V);
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} else {
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AM.Base.Reg = getRegForValue(V);
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if (AM.Base.Reg == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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}
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return true;
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}
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/// X86SelectStore - Select and emit code to implement store instructions.
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bool X86FastISel::X86SelectStore(Instruction* I) {
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MVT VT;
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if (!isTypeLegal(I->getOperand(0)->getType(), TLI, VT))
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return false;
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unsigned Val = getRegForValue(I->getOperand(0));
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if (Val == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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X86AddressMode AM;
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if (!X86SelectAddress(I->getOperand(1), AM))
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return false;
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return X86FastEmitStore(VT, Val, AM);
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}
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/// X86SelectLoad - Select and emit code to implement load instructions.
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///
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bool X86FastISel::X86SelectLoad(Instruction *I) {
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MVT VT;
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if (!isTypeLegal(I->getType(), TLI, VT))
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return false;
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X86AddressMode AM;
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if (!X86SelectAddress(I->getOperand(0), AM))
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return false;
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unsigned ResultReg = 0;
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if (X86FastEmitLoad(VT, AM, ResultReg)) {
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UpdateValueMap(I, ResultReg);
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return true;
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}
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return false;
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}
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bool X86FastISel::X86SelectCmp(Instruction *I) {
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CmpInst *CI = cast<CmpInst>(I);
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MVT VT = TLI.getValueType(I->getOperand(0)->getType());
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if (!TLI.isTypeLegal(VT))
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return false;
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unsigned Op0Reg = getRegForValue(CI->getOperand(0));
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if (Op0Reg == 0) return false;
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unsigned Op1Reg = getRegForValue(CI->getOperand(1));
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if (Op1Reg == 0) return false;
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unsigned Opc;
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switch (VT.getSimpleVT()) {
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case MVT::i8: Opc = X86::CMP8rr; break;
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case MVT::i16: Opc = X86::CMP16rr; break;
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case MVT::i32: Opc = X86::CMP32rr; break;
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case MVT::i64: Opc = X86::CMP64rr; break;
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case MVT::f32: Opc = X86::UCOMISSrr; break;
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case MVT::f64: Opc = X86::UCOMISDrr; break;
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default: return false;
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}
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unsigned ResultReg = createResultReg(&X86::GR8RegClass);
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switch (CI->getPredicate()) {
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case CmpInst::FCMP_OEQ: {
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unsigned EReg = createResultReg(&X86::GR8RegClass);
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unsigned NPReg = createResultReg(&X86::GR8RegClass);
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETEr), EReg);
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BuildMI(MBB, TII.get(X86::SETNPr), NPReg);
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BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
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break;
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}
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case CmpInst::FCMP_UNE: {
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unsigned NEReg = createResultReg(&X86::GR8RegClass);
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unsigned PReg = createResultReg(&X86::GR8RegClass);
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETNEr), NEReg);
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BuildMI(MBB, TII.get(X86::SETPr), PReg);
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BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
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break;
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}
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case CmpInst::FCMP_OGT:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
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break;
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case CmpInst::FCMP_OGE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
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break;
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case CmpInst::FCMP_OLT:
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BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
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BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
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break;
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case CmpInst::FCMP_OLE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
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BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
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break;
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case CmpInst::FCMP_ONE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETNEr), ResultReg);
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break;
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case CmpInst::FCMP_ORD:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETNPr), ResultReg);
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break;
|
|
case CmpInst::FCMP_UNO:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETPr), ResultReg);
|
|
break;
|
|
case CmpInst::FCMP_UEQ:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETEr), ResultReg);
|
|
break;
|
|
case CmpInst::FCMP_UGT:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
|
|
BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
|
|
break;
|
|
case CmpInst::FCMP_UGE:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
|
|
BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
|
|
break;
|
|
case CmpInst::FCMP_ULT:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
|
|
break;
|
|
case CmpInst::FCMP_ULE:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
|
|
break;
|
|
case CmpInst::ICMP_EQ:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETEr), ResultReg);
|
|
break;
|
|
case CmpInst::ICMP_NE:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETNEr), ResultReg);
|
|
break;
|
|
case CmpInst::ICMP_UGT:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
|
|
break;
|
|
case CmpInst::ICMP_UGE:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
|
|
break;
|
|
case CmpInst::ICMP_ULT:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
|
|
break;
|
|
case CmpInst::ICMP_ULE:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
|
|
break;
|
|
case CmpInst::ICMP_SGT:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETGr), ResultReg);
|
|
break;
|
|
case CmpInst::ICMP_SGE:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETGEr), ResultReg);
|
|
break;
|
|
case CmpInst::ICMP_SLT:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETLr), ResultReg);
|
|
break;
|
|
case CmpInst::ICMP_SLE:
|
|
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
|
|
BuildMI(MBB, TII.get(X86::SETLEr), ResultReg);
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool X86FastISel::X86SelectZExt(Instruction *I) {
|
|
// Special-case hack: The only i1 values we know how to produce currently
|
|
// set the upper bits of an i8 value to zero.
|
|
if (I->getType() == Type::Int8Ty &&
|
|
I->getOperand(0)->getType() == Type::Int1Ty) {
|
|
unsigned ResultReg = getRegForValue(I->getOperand(0));
|
|
if (ResultReg == 0) return false;
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool X86FastISel::X86SelectBranch(Instruction *I) {
|
|
BranchInst *BI = cast<BranchInst>(I);
|
|
// Unconditional branches are selected by tablegen-generated code.
|
|
unsigned OpReg = getRegForValue(BI->getCondition());
|
|
if (OpReg == 0) return false;
|
|
MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
|
|
MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
|
|
|
|
BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
|
|
BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
|
|
BuildMI(MBB, TII.get(X86::JMP)).addMBB(FalseMBB);
|
|
|
|
MBB->addSuccessor(TrueMBB);
|
|
MBB->addSuccessor(FalseMBB);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool X86FastISel::X86SelectShift(Instruction *I) {
|
|
unsigned CReg = 0;
|
|
unsigned Opc = 0;
|
|
const TargetRegisterClass *RC = NULL;
|
|
if (I->getType() == Type::Int8Ty) {
|
|
CReg = X86::CL;
|
|
RC = &X86::GR8RegClass;
|
|
switch (I->getOpcode()) {
|
|
case Instruction::LShr: Opc = X86::SHR8rCL; break;
|
|
case Instruction::AShr: Opc = X86::SAR8rCL; break;
|
|
case Instruction::Shl: Opc = X86::SHL8rCL; break;
|
|
default: return false;
|
|
}
|
|
} else if (I->getType() == Type::Int16Ty) {
|
|
CReg = X86::CX;
|
|
RC = &X86::GR16RegClass;
|
|
switch (I->getOpcode()) {
|
|
case Instruction::LShr: Opc = X86::SHR16rCL; break;
|
|
case Instruction::AShr: Opc = X86::SAR16rCL; break;
|
|
case Instruction::Shl: Opc = X86::SHL16rCL; break;
|
|
default: return false;
|
|
}
|
|
} else if (I->getType() == Type::Int32Ty) {
|
|
CReg = X86::ECX;
|
|
RC = &X86::GR32RegClass;
|
|
switch (I->getOpcode()) {
|
|
case Instruction::LShr: Opc = X86::SHR32rCL; break;
|
|
case Instruction::AShr: Opc = X86::SAR32rCL; break;
|
|
case Instruction::Shl: Opc = X86::SHL32rCL; break;
|
|
default: return false;
|
|
}
|
|
} else if (I->getType() == Type::Int64Ty) {
|
|
CReg = X86::RCX;
|
|
RC = &X86::GR64RegClass;
|
|
switch (I->getOpcode()) {
|
|
case Instruction::LShr: Opc = X86::SHR64rCL; break;
|
|
case Instruction::AShr: Opc = X86::SAR64rCL; break;
|
|
case Instruction::Shl: Opc = X86::SHL64rCL; break;
|
|
default: return false;
|
|
}
|
|
} else {
|
|
return false;
|
|
}
|
|
|
|
MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
|
|
if (VT == MVT::Other || !TLI.isTypeLegal(VT))
|
|
return false;
|
|
|
|
unsigned Op0Reg = getRegForValue(I->getOperand(0));
|
|
if (Op0Reg == 0) return false;
|
|
unsigned Op1Reg = getRegForValue(I->getOperand(1));
|
|
if (Op1Reg == 0) return false;
|
|
TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
|
|
unsigned ResultReg = createResultReg(RC);
|
|
BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op0Reg);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool X86FastISel::X86SelectSelect(Instruction *I) {
|
|
const Type *Ty = I->getType();
|
|
if (isa<PointerType>(Ty))
|
|
Ty = TLI.getTargetData()->getIntPtrType();
|
|
|
|
unsigned Opc = 0;
|
|
const TargetRegisterClass *RC = NULL;
|
|
if (Ty == Type::Int16Ty) {
|
|
Opc = X86::CMOVE16rr;
|
|
RC = &X86::GR16RegClass;
|
|
} else if (Ty == Type::Int32Ty) {
|
|
Opc = X86::CMOVE32rr;
|
|
RC = &X86::GR32RegClass;
|
|
} else if (Ty == Type::Int64Ty) {
|
|
Opc = X86::CMOVE64rr;
|
|
RC = &X86::GR64RegClass;
|
|
} else {
|
|
return false;
|
|
}
|
|
|
|
MVT VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
|
|
if (VT == MVT::Other || !TLI.isTypeLegal(VT))
|
|
return false;
|
|
|
|
unsigned Op0Reg = getRegForValue(I->getOperand(0));
|
|
if (Op0Reg == 0) return false;
|
|
unsigned Op1Reg = getRegForValue(I->getOperand(1));
|
|
if (Op1Reg == 0) return false;
|
|
unsigned Op2Reg = getRegForValue(I->getOperand(2));
|
|
if (Op2Reg == 0) return false;
|
|
|
|
BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
|
|
unsigned ResultReg = createResultReg(RC);
|
|
BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool X86FastISel::X86SelectFPExt(Instruction *I) {
|
|
if (Subtarget->hasSSE2()) {
|
|
if (I->getType() == Type::DoubleTy) {
|
|
Value *V = I->getOperand(0);
|
|
if (V->getType() == Type::FloatTy) {
|
|
unsigned OpReg = getRegForValue(V);
|
|
if (OpReg == 0) return false;
|
|
unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
|
|
BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
|
|
if (Subtarget->hasSSE2()) {
|
|
if (I->getType() == Type::FloatTy) {
|
|
Value *V = I->getOperand(0);
|
|
if (V->getType() == Type::DoubleTy) {
|
|
unsigned OpReg = getRegForValue(V);
|
|
if (OpReg == 0) return false;
|
|
unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
|
|
BuildMI(MBB, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool X86FastISel::X86SelectTrunc(Instruction *I) {
|
|
if (Subtarget->is64Bit())
|
|
// All other cases should be handled by the tblgen generated code.
|
|
return false;
|
|
MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
|
|
MVT DstVT = TLI.getValueType(I->getType());
|
|
if (DstVT != MVT::i8)
|
|
// All other cases should be handled by the tblgen generated code.
|
|
return false;
|
|
if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
|
|
// All other cases should be handled by the tblgen generated code.
|
|
return false;
|
|
|
|
unsigned InputReg = getRegForValue(I->getOperand(0));
|
|
if (!InputReg)
|
|
// Unhandled operand. Halt "fast" selection and bail.
|
|
return false;
|
|
|
|
// First issue a copy to GR16_ or GR32_.
|
|
unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16to16_ : X86::MOV32to32_;
|
|
const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
|
|
? X86::GR16_RegisterClass : X86::GR32_RegisterClass;
|
|
unsigned CopyReg = createResultReg(CopyRC);
|
|
BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg);
|
|
|
|
// Then issue an extract_subreg.
|
|
unsigned ResultReg = FastEmitInst_extractsubreg(CopyReg,1); // x86_subreg_8bit
|
|
if (!ResultReg)
|
|
return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool X86FastISel::X86SelectCall(Instruction *I) {
|
|
CallInst *CI = cast<CallInst>(I);
|
|
Value *Callee = I->getOperand(0);
|
|
|
|
// Can't handle inline asm yet.
|
|
if (isa<InlineAsm>(Callee))
|
|
return false;
|
|
|
|
// FIXME: Handle some intrinsics.
|
|
if (Function *F = CI->getCalledFunction()) {
|
|
if (F->isDeclaration() &&F->getIntrinsicID())
|
|
return false;
|
|
}
|
|
|
|
// Materialize callee address in a register. FIXME: GV address can be
|
|
// handled with a CALLpcrel32 instead.
|
|
unsigned CalleeOp = getRegForValue(Callee);
|
|
if (CalleeOp == 0) {
|
|
if (!isa<Constant>(Callee) || !X86SelectConstAddr(Callee, CalleeOp, true))
|
|
// Unhandled operand. Halt "fast" selection and bail.
|
|
return false;
|
|
}
|
|
|
|
// Handle only C and fastcc calling conventions for now.
|
|
CallSite CS(CI);
|
|
unsigned CC = CS.getCallingConv();
|
|
if (CC != CallingConv::C &&
|
|
CC != CallingConv::Fast &&
|
|
CC != CallingConv::X86_FastCall)
|
|
return false;
|
|
|
|
// Let SDISel handle vararg functions.
|
|
const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
|
|
const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
|
|
if (FTy->isVarArg())
|
|
return false;
|
|
|
|
// Handle *simple* calls for now.
|
|
const Type *RetTy = CS.getType();
|
|
MVT RetVT;
|
|
if (!isTypeLegal(RetTy, TLI, RetVT, true))
|
|
return false;
|
|
|
|
// Allow calls which produce i1 results.
|
|
bool AndToI1 = false;
|
|
if (RetVT == MVT::i1) {
|
|
RetVT = MVT::i8;
|
|
AndToI1 = true;
|
|
}
|
|
|
|
// Deal with call operands first.
|
|
SmallVector<unsigned, 4> Args;
|
|
SmallVector<MVT, 4> ArgVTs;
|
|
SmallVector<ISD::ArgFlagsTy, 4> ArgFlags;
|
|
Args.reserve(CS.arg_size());
|
|
ArgVTs.reserve(CS.arg_size());
|
|
ArgFlags.reserve(CS.arg_size());
|
|
for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
|
|
i != e; ++i) {
|
|
unsigned Arg = getRegForValue(*i);
|
|
if (Arg == 0)
|
|
return false;
|
|
ISD::ArgFlagsTy Flags;
|
|
unsigned AttrInd = i - CS.arg_begin() + 1;
|
|
if (CS.paramHasAttr(AttrInd, ParamAttr::SExt))
|
|
Flags.setSExt();
|
|
if (CS.paramHasAttr(AttrInd, ParamAttr::ZExt))
|
|
Flags.setZExt();
|
|
|
|
// FIXME: Only handle *easy* calls for now.
|
|
if (CS.paramHasAttr(AttrInd, ParamAttr::InReg) ||
|
|
CS.paramHasAttr(AttrInd, ParamAttr::StructRet) ||
|
|
CS.paramHasAttr(AttrInd, ParamAttr::Nest) ||
|
|
CS.paramHasAttr(AttrInd, ParamAttr::ByVal))
|
|
return false;
|
|
|
|
const Type *ArgTy = (*i)->getType();
|
|
MVT ArgVT;
|
|
if (!isTypeLegal(ArgTy, TLI, ArgVT))
|
|
return false;
|
|
unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
|
|
Flags.setOrigAlign(OriginalAlignment);
|
|
|
|
Args.push_back(Arg);
|
|
ArgVTs.push_back(ArgVT);
|
|
ArgFlags.push_back(Flags);
|
|
}
|
|
|
|
// Analyze operands of the call, assigning locations to each operand.
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
|
CCState CCInfo(CC, false, TM, ArgLocs);
|
|
CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
|
|
|
|
// Get a count of how many bytes are to be pushed on the stack.
|
|
unsigned NumBytes = CCInfo.getNextStackOffset();
|
|
|
|
// Issue CALLSEQ_START
|
|
BuildMI(MBB, TII.get(X86::ADJCALLSTACKDOWN)).addImm(NumBytes);
|
|
|
|
// Process argumenet: walk the register/memloc assignments, inserting
|
|
// copies / loads.
|
|
SmallVector<unsigned, 4> RegArgs;
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
CCValAssign &VA = ArgLocs[i];
|
|
unsigned Arg = Args[VA.getValNo()];
|
|
MVT ArgVT = ArgVTs[VA.getValNo()];
|
|
|
|
// Promote the value if needed.
|
|
switch (VA.getLocInfo()) {
|
|
default: assert(0 && "Unknown loc info!");
|
|
case CCValAssign::Full: break;
|
|
case CCValAssign::SExt: {
|
|
bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
|
|
Arg, ArgVT, Arg);
|
|
assert(Emitted && "Failed to emit a sext!");
|
|
ArgVT = VA.getLocVT();
|
|
break;
|
|
}
|
|
case CCValAssign::ZExt: {
|
|
bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
|
|
Arg, ArgVT, Arg);
|
|
assert(Emitted && "Failed to emit a zext!");
|
|
ArgVT = VA.getLocVT();
|
|
break;
|
|
}
|
|
case CCValAssign::AExt: {
|
|
bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
|
|
Arg, ArgVT, Arg);
|
|
if (!Emitted)
|
|
Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
|
|
Arg, ArgVT, Arg);
|
|
if (!Emitted)
|
|
Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
|
|
Arg, ArgVT, Arg);
|
|
|
|
assert(Emitted && "Failed to emit a aext!");
|
|
ArgVT = VA.getLocVT();
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (VA.isRegLoc()) {
|
|
TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
|
|
bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
|
|
Arg, RC, RC);
|
|
assert(Emitted && "Failed to emit a copy instruction!");
|
|
RegArgs.push_back(VA.getLocReg());
|
|
} else {
|
|
unsigned LocMemOffset = VA.getLocMemOffset();
|
|
X86AddressMode AM;
|
|
AM.Base.Reg = StackPtr;
|
|
AM.Disp = LocMemOffset;
|
|
X86FastEmitStore(ArgVT, Arg, AM);
|
|
}
|
|
}
|
|
|
|
// Issue the call.
|
|
unsigned CallOpc = CalleeOp
|
|
? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r)
|
|
: (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
|
|
MachineInstrBuilder MIB = CalleeOp
|
|
? BuildMI(MBB, TII.get(CallOpc)).addReg(CalleeOp)
|
|
:BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(cast<GlobalValue>(Callee));
|
|
// Add implicit physical register uses to the call.
|
|
while (!RegArgs.empty()) {
|
|
MIB.addReg(RegArgs.back());
|
|
RegArgs.pop_back();
|
|
}
|
|
|
|
// Issue CALLSEQ_END
|
|
BuildMI(MBB, TII.get(X86::ADJCALLSTACKUP)).addImm(NumBytes).addImm(0);
|
|
|
|
// Now handle call return value (if any).
|
|
if (RetVT.getSimpleVT() != MVT::isVoid) {
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
CCState CCInfo(CC, false, TM, RVLocs);
|
|
CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
|
|
MVT CopyVT = RVLocs[0].getValVT();
|
|
TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
|
|
TargetRegisterClass *SrcRC = DstRC;
|
|
|
|
// If this is a call to a function that returns an fp value on the x87 fp
|
|
// stack, but where we prefer to use the value in xmm registers, copy it
|
|
// out as F80 and use a truncate to move it from fp stack reg to xmm reg.
|
|
if ((RVLocs[0].getLocReg() == X86::ST0 ||
|
|
RVLocs[0].getLocReg() == X86::ST1) &&
|
|
isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
|
|
CopyVT = MVT::f80;
|
|
SrcRC = X86::RSTRegisterClass;
|
|
DstRC = X86::RFP80RegisterClass;
|
|
}
|
|
|
|
unsigned ResultReg = createResultReg(DstRC);
|
|
bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
RVLocs[0].getLocReg(), DstRC, SrcRC);
|
|
assert(Emitted && "Failed to emit a copy instruction!");
|
|
if (CopyVT != RVLocs[0].getValVT()) {
|
|
// Round the F80 the right size, which also moves to the appropriate xmm
|
|
// register. This is accomplished by storing the F80 value in memory and
|
|
// then loading it back. Ewww...
|
|
MVT ResVT = RVLocs[0].getValVT();
|
|
unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
|
|
unsigned MemSize = ResVT.getSizeInBits()/8;
|
|
int FI = MFI.CreateStackObject(MemSize, MemSize);
|
|
addFrameReference(BuildMI(MBB, TII.get(Opc)), FI).addReg(ResultReg);
|
|
DstRC = ResVT == MVT::f32
|
|
? X86::FR32RegisterClass : X86::FR64RegisterClass;
|
|
Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
|
|
ResultReg = createResultReg(DstRC);
|
|
addFrameReference(BuildMI(MBB, TII.get(Opc), ResultReg), FI);
|
|
}
|
|
|
|
if (AndToI1) {
|
|
// Mask out all but lowest bit for some call which produces an i1.
|
|
unsigned AndResult = createResultReg(X86::GR8RegisterClass);
|
|
BuildMI(MBB, TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
|
|
ResultReg = AndResult;
|
|
}
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
bool
|
|
X86FastISel::TargetSelectInstruction(Instruction *I) {
|
|
switch (I->getOpcode()) {
|
|
default: break;
|
|
case Instruction::Load:
|
|
return X86SelectLoad(I);
|
|
case Instruction::Store:
|
|
return X86SelectStore(I);
|
|
case Instruction::ICmp:
|
|
case Instruction::FCmp:
|
|
return X86SelectCmp(I);
|
|
case Instruction::ZExt:
|
|
return X86SelectZExt(I);
|
|
case Instruction::Br:
|
|
return X86SelectBranch(I);
|
|
case Instruction::Call:
|
|
return X86SelectCall(I);
|
|
case Instruction::LShr:
|
|
case Instruction::AShr:
|
|
case Instruction::Shl:
|
|
return X86SelectShift(I);
|
|
case Instruction::Select:
|
|
return X86SelectSelect(I);
|
|
case Instruction::Trunc:
|
|
return X86SelectTrunc(I);
|
|
case Instruction::FPExt:
|
|
return X86SelectFPExt(I);
|
|
case Instruction::FPTrunc:
|
|
return X86SelectFPTrunc(I);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
|
|
// Can't handle PIC-mode yet.
|
|
if (TM.getRelocationModel() == Reloc::PIC_)
|
|
return 0;
|
|
|
|
MVT VT;
|
|
if (!isTypeLegal(C->getType(), TLI, VT))
|
|
return false;
|
|
|
|
// Get opcode and regclass of the output for the given load instruction.
|
|
unsigned Opc = 0;
|
|
const TargetRegisterClass *RC = NULL;
|
|
switch (VT.getSimpleVT()) {
|
|
default: return false;
|
|
case MVT::i8:
|
|
Opc = X86::MOV8rm;
|
|
RC = X86::GR8RegisterClass;
|
|
break;
|
|
case MVT::i16:
|
|
Opc = X86::MOV16rm;
|
|
RC = X86::GR16RegisterClass;
|
|
break;
|
|
case MVT::i32:
|
|
Opc = X86::MOV32rm;
|
|
RC = X86::GR32RegisterClass;
|
|
break;
|
|
case MVT::i64:
|
|
// Must be in x86-64 mode.
|
|
Opc = X86::MOV64rm;
|
|
RC = X86::GR64RegisterClass;
|
|
break;
|
|
case MVT::f32:
|
|
if (Subtarget->hasSSE1()) {
|
|
Opc = X86::MOVSSrm;
|
|
RC = X86::FR32RegisterClass;
|
|
} else {
|
|
Opc = X86::LD_Fp32m;
|
|
RC = X86::RFP32RegisterClass;
|
|
}
|
|
break;
|
|
case MVT::f64:
|
|
if (Subtarget->hasSSE2()) {
|
|
Opc = X86::MOVSDrm;
|
|
RC = X86::FR64RegisterClass;
|
|
} else {
|
|
Opc = X86::LD_Fp64m;
|
|
RC = X86::RFP64RegisterClass;
|
|
}
|
|
break;
|
|
case MVT::f80:
|
|
Opc = X86::LD_Fp80m;
|
|
RC = X86::RFP80RegisterClass;
|
|
break;
|
|
}
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
|
if (isa<GlobalValue>(C)) {
|
|
if (X86SelectConstAddr(C, ResultReg, false, true))
|
|
return ResultReg;
|
|
return 0;
|
|
}
|
|
|
|
// MachineConstantPool wants an explicit alignment.
|
|
unsigned Align =
|
|
TM.getTargetData()->getPreferredTypeAlignmentShift(C->getType());
|
|
if (Align == 0) {
|
|
// Alignment of vector types. FIXME!
|
|
Align = TM.getTargetData()->getABITypeSize(C->getType());
|
|
Align = Log2_64(Align);
|
|
}
|
|
|
|
unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
|
|
addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset);
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
|
|
X86AddressMode AM;
|
|
if (!X86SelectAddress(C, AM))
|
|
return 0;
|
|
unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
|
|
TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
|
|
unsigned ResultReg = createResultReg(RC);
|
|
addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
|
|
return ResultReg;
|
|
}
|
|
|
|
namespace llvm {
|
|
llvm::FastISel *X86::createFastISel(MachineFunction &mf,
|
|
DenseMap<const Value *, unsigned> &vm,
|
|
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
|
|
DenseMap<const AllocaInst *, int> &am) {
|
|
return new X86FastISel(mf, vm, bm, am);
|
|
}
|
|
}
|