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https://github.com/c64scene-ar/llvm-6502.git
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4f83e2ca5d
Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208327 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
1.9 KiB
ArmAsm
50 lines
1.9 KiB
ArmAsm
# Instructions that should be valid but currently fail for known reasons (e.g.
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# they aren't implemented yet).
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# This test is set up to XPASS if any instruction generates an encoding.
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#
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# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | not FileCheck %s
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# CHECK-NOT: encoding
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# XFAIL: *
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.set noat
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c.eq.d $fcc1,$f15,$f15
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c.eq.s $fcc5,$f24,$f17
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c.f.d $fcc4,$f11,$f21
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c.f.s $fcc4,$f30,$f7
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c.le.d $fcc4,$f18,$f1
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c.le.s $fcc6,$f24,$f4
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c.lt.d $fcc3,$f9,$f3
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c.lt.s $fcc2,$f17,$f14
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c.nge.d $fcc5,$f21,$f16
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c.nge.s $fcc3,$f11,$f8
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c.ngl.s $fcc2,$f31,$f23
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c.ngle.s $fcc2,$f18,$f23
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c.ngt.d $fcc4,$f24,$f7
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c.ngt.s $fcc5,$f8,$f13
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c.ole.d $fcc2,$f16,$f31
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c.ole.s $fcc3,$f7,$f20
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c.olt.d $fcc4,$f19,$f28
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c.olt.s $fcc6,$f20,$f7
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c.seq.d $fcc4,$f31,$f7
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c.seq.s $fcc7,$f1,$f25
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c.ueq.d $fcc4,$f13,$f25
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c.ueq.s $fcc6,$f3,$f30
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c.ule.d $fcc7,$f25,$f18
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c.ule.s $fcc7,$f21,$f30
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c.ult.d $fcc6,$f6,$f17
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c.ult.s $fcc7,$f24,$f10
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c.un.d $fcc6,$f23,$f24
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c.un.s $fcc1,$f30,$f4
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madd.d $f18,$f19,$f26,$f20
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madd.s $f1,$f31,$f19,$f25
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msub.d $f10,$f1,$f31,$f18
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msub.s $f12,$f19,$f10,$f16
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nmadd.d $f18,$f9,$f14,$f19
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nmadd.s $f0,$f5,$f25,$f12
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nmsub.d $f30,$f8,$f16,$f30
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nmsub.s $f1,$f24,$f19,$f4
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recip.d $f19,$f6
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recip.s $f3,$f30
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rsqrt.d $f3,$f28
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rsqrt.s $f4,$f8
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