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Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
2.0 KiB
TableGen
53 lines
2.0 KiB
TableGen
//===- Blackfin.td - Describe the Blackfin Target Machine --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Blackfin Subtarget features.
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//===----------------------------------------------------------------------===//
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def FeatureSSYNC : SubtargetFeature<"ssync","ssyncWorkaround", "true",
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"Work around SSYNC bugs">;
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "BlackfinRegisterInfo.td"
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include "BlackfinCallingConv.td"
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include "BlackfinInstrInfo.td"
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def BlackfinInstrInfo : InstrInfo {}
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//===----------------------------------------------------------------------===//
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// Blackfin processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", [FeatureSSYNC]>;
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def Blackfin : Target {
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// Pull in Instruction Info:
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let InstructionSet = BlackfinInstrInfo;
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}
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