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Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
123 lines
4.4 KiB
Org Mode
123 lines
4.4 KiB
Org Mode
//===-- README.txt - Notes for Blackfin Target ------------------*- org -*-===//
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* Condition codes
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** DONE Problem with asymmetric SETCC operations
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The instruction
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CC = R0 < 2
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is not symmetric - there is no R0 > 2 instruction. On the other hand, IF CC
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JUMP can take both CC and !CC as a condition. We cannot pattern-match (brcond
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(not cc), target), the DAG optimizer removes that kind of thing.
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This is handled by creating a pseudo-register NCC that aliases CC. Register
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classes JustCC and NotCC are used to control the inversion of CC.
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** DONE CC as an i32 register
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The AnyCC register class pretends to hold i32 values. It can only represent the
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values 0 and 1, but we can copy to and from the D class. This hack makes it
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possible to represent the setcc instruction without having i1 as a legal type.
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In most cases, the CC register is set by a "CC = .." or BITTST instruction, and
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then used in a conditional branch or move. The code generator thinks it is
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moving 32 bits, but the value stays in CC. In other cases, the result of a
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comparison is actually used as am i32 number, and CC will be copied to a D
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register.
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* Stack frames
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** TODO Use Push/Pop instructions
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We should use the push/pop instructions when saving callee-saved
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registers. The are smaller, and we may even use push multiple instructions.
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** TODO requiresRegisterScavenging
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We need more intelligence in determining when the scavenger is needed. We
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should keep track of:
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- Spilling D16 registers
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- Spilling AnyCC registers
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* Assembler
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** TODO Implement PrintGlobalVariable
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** TODO Remove LOAD32sym
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It's a hack combining two instructions by concatenation.
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* Inline Assembly
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** TODO Support all register classes
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* DAG combiner
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** Create test case for each Illegal SETCC case
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The DAG combiner may someimes produce illegal i16 SETCC instructions.
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*** TODO SETCC (ctlz x), 5) == const
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*** TODO SETCC (and load, const) == const
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*** DONE SETCC (zext x) == const
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*** TODO SETCC (sext x) == const
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* Instruction selection
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** TODO Better imediate constants
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Like ARM, build constants as small imm + shift.
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** TODO Implement cycle counter
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We have CYCLES and CYCLES2 registers, but the readcyclecounter intrinsic wants
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to return i64, and the code generator doesn't know how to legalize that.
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** TODO Instruction alternatives
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Some instructions come in different variants for example:
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D = D + D
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P = P + P
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Cross combinations are not allowed:
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P = D + D (bad)
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Similarly for the subreg pseudo-instructions:
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D16L = EXTRACT_SUBREG D16, bfin_subreg_lo16
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P16L = EXTRACT_SUBREG P16, bfin_subreg_lo16
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We want to take advantage of the alternative instructions. This could be done by
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changing the DAG after instruction selection.
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** Multipatterns for load/store
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We should try to identify multipatterns for load and store instructions. The
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available instruction matrix is a bit irregular.
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Loads:
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| Addr | D | P | D 16z | D 16s | D16 | D 8z | D 8s |
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|------------+---+---+-------+-------+-----+------+------|
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| P | * | * | * | * | * | * | * |
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| P++ | * | * | * | * | | * | * |
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| P-- | * | * | * | * | | * | * |
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| P+uimm5m2 | | | * | * | | | |
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| P+uimm6m4 | * | * | | | | | |
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| P+imm16 | | | | | | * | * |
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| P+imm17m2 | | | * | * | | | |
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| P+imm18m4 | * | * | | | | | |
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| P++P | * | | * | * | * | | |
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| FP-uimm7m4 | * | * | | | | | |
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| I | * | | | | * | | |
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| I++ | * | | | | * | | |
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| I-- | * | | | | * | | |
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| I++M | * | | | | | | |
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Stores:
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| Addr | D | P | D16H | D16L | D 8 |
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|------------+---+---+------+------+-----|
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| P | * | * | * | * | * |
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| P++ | * | * | | * | * |
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| P-- | * | * | | * | * |
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| P+uimm5m2 | | | | * | |
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| P+uimm6m4 | * | * | | | |
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| P+imm16 | | | | | * |
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| P+imm17m2 | | | | * | |
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| P+imm18m4 | * | * | | | |
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| P++P | * | | * | * | |
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| FP-uimm7m4 | * | * | | | |
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| I | * | | * | * | |
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| I++ | * | | * | * | |
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| I-- | * | | * | * | |
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| I++M | * | | | | |
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