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https://github.com/c64scene-ar/llvm-6502.git
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047bbafb99
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4372 91177308-0d34-0410-b5e6-96231b3b80d8
737 lines
29 KiB
C++
737 lines
29 KiB
C++
//===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
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//
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// This file defines stuff that is to be private to the Sparc backend, but is
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// shared among different portions of the backend.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARC_INTERNALS_H
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#define SPARC_INTERNALS_H
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineSchedInfo.h"
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#include "llvm/Target/MachineFrameInfo.h"
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#include "llvm/Target/MachineCacheInfo.h"
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#include "llvm/Target/MachineRegInfo.h"
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#include "llvm/Target/MachineOptInfo.h"
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#include "llvm/Type.h"
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#include <sys/types.h>
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class LiveRange;
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class UltraSparc;
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class PhyRegAlloc;
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class Pass;
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enum SparcInstrSchedClass {
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SPARC_NONE, /* Instructions with no scheduling restrictions */
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SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
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SPARC_IEU0, /* Integer class IEU0 */
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SPARC_IEU1, /* Integer class IEU1 */
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SPARC_FPM, /* FP Multiply or Divide instructions */
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SPARC_FPA, /* All other FP instructions */
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SPARC_CTI, /* Control-transfer instructions */
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SPARC_LD, /* Load instructions */
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SPARC_ST, /* Store instructions */
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SPARC_SINGLE, /* Instructions that must issue by themselves */
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SPARC_INV, /* This should stay at the end for the next value */
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SPARC_NUM_SCHED_CLASSES = SPARC_INV
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};
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//---------------------------------------------------------------------------
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// enum SparcMachineOpCode.
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// const MachineInstrDescriptor SparcMachineInstrDesc[]
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//
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// Purpose:
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// Description of UltraSparc machine instructions.
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//
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//---------------------------------------------------------------------------
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enum SparcMachineOpCode {
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#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
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ENUM,
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#include "SparcInstr.def"
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// End-of-array marker
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INVALID_OPCODE,
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NUM_REAL_OPCODES = PHI, // number of valid opcodes
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NUM_TOTAL_OPCODES = INVALID_OPCODE
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};
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// Array of machine instruction descriptions...
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extern const MachineInstrDescriptor SparcMachineInstrDesc[];
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//---------------------------------------------------------------------------
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// class UltraSparcInstrInfo
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//
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// Purpose:
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// Information about individual instructions.
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// Most information is stored in the SparcMachineInstrDesc array above.
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// Other information is computed on demand, and most such functions
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// default to member functions in base class MachineInstrInfo.
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//---------------------------------------------------------------------------
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struct UltraSparcInstrInfo : public MachineInstrInfo {
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UltraSparcInstrInfo();
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//
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// All immediate constants are in position 1 except the
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// store instructions and SETxx.
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//
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virtual int getImmedConstantPos(MachineOpCode opCode) const {
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bool ignore;
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if (this->maxImmedConstant(opCode, ignore) != 0)
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{
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assert(! this->isStore((MachineOpCode) STB - 1)); // 1st store opcode
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assert(! this->isStore((MachineOpCode) STXFSR+1));// last store opcode
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if (opCode==SETSW || opCode==SETUW || opCode==SETX || opCode==SETHI)
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return 0;
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if (opCode >= STB && opCode <= STXFSR)
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return 2;
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return 1;
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}
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else
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return -1;
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}
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virtual bool hasResultInterlock (MachineOpCode opCode) const
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{
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// All UltraSPARC instructions have interlocks (note that delay slots
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// are not considered here).
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// However, instructions that use the result of an FCMP produce a
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// 9-cycle stall if they are issued less than 3 cycles after the FCMP.
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// Force the compiler to insert a software interlock (i.e., gap of
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// 2 other groups, including NOPs if necessary).
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return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
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}
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//-------------------------------------------------------------------------
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// Queries about representation of LLVM quantities (e.g., constants)
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//-------------------------------------------------------------------------
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virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
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const Instruction* I) const;
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//-------------------------------------------------------------------------
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// Code generation support for creating individual machine instructions
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//-------------------------------------------------------------------------
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// Get certain common op codes for the current target. This and all the
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// Create* methods below should be moved to a machine code generation class
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//
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virtual MachineOpCode getNOPOpCode() const { return NOP; }
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// Create an instruction sequence to put the constant `val' into
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// the virtual register `dest'. `val' may be a Constant or a
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// GlobalValue, viz., the constant address of a global variable or function.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToLoadConst(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create an instruction sequence to copy an integer value `val'
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// to a floating point value `dest' by copying to memory and back.
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// val must be an integral type. dest must be a Float or Double.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Similarly, create an instruction sequence to copy an FP value
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// `val' to an integer value `dest' by copying to memory and back.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create instruction(s) to copy src to dest, for arbitrary types
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCopyInstructionsByType(const TargetMachine& target,
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Function* F,
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Value* src,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create instruction sequence to produce a sign-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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// The generated instructions are appended to `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateSignExtensionInstructions(const TargetMachine& target,
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Function* F,
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Value* srcVal,
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Value* destVal,
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unsigned int numLowBits,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create instruction sequence to produce a zero-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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// The generated instructions are appended to `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
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Function* F,
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Value* srcVal,
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Value* destVal,
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unsigned int numLowBits,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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};
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//----------------------------------------------------------------------------
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// class UltraSparcRegInfo
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//
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// This class implements the virtual class MachineRegInfo for Sparc.
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//
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//----------------------------------------------------------------------------
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class UltraSparcRegInfo : public MachineRegInfo {
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// The actual register classes in the Sparc
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//
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enum RegClassIDs {
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IntRegClassID, // Integer
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FloatRegClassID, // Float (both single/double)
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IntCCRegClassID, // Int Condition Code
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FloatCCRegClassID // Float Condition code
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};
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// Type of registers available in Sparc. There can be several reg types
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// in the same class. For instace, the float reg class has Single/Double
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// types
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//
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enum RegTypes {
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IntRegType,
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FPSingleRegType,
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FPDoubleRegType,
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IntCCRegType,
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FloatCCRegType
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};
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// **** WARNING: If the above enum order is changed, also modify
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// getRegisterClassOfValue method below since it assumes this particular
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// order for efficiency.
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// Number of registers used for passing int args (usually 6: %o0 - %o5)
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//
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unsigned const NumOfIntArgRegs;
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// Number of registers used for passing float args (usually 32: %f0 - %f31)
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//
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unsigned const NumOfFloatArgRegs;
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// An out of bound register number that can be used to initialize register
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// numbers. Useful for error detection.
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//
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int const InvalidRegNum;
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// ======================== Private Methods =============================
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// The following methods are used to color special live ranges (e.g.
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// function args and return values etc.) with specific hardware registers
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// as required. See SparcRegInfo.cpp for the implementation.
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//
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void suggestReg4RetAddr(MachineInstr *RetMI,
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LiveRangeInfo &LRI) const;
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void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
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void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
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PhyRegAlloc &PRA, LiveRange* LR,
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unsigned regType, unsigned RegClassID,
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int UniArgReg, unsigned int argNo,
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std::vector<MachineInstr *>& AddedInstrnsBefore)
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const;
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// The following 4 methods are used to find the RegType (see enum above)
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// for a reg class and a given primitive type, a LiveRange, a Value,
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// or a particular machine register.
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// The fifth function gives the reg class of the given RegType.
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//
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int getRegType(unsigned regClassID, const Type* type) const;
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int getRegType(const LiveRange *LR) const;
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int getRegType(const Value *Val) const;
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int getRegType(int unifiedRegNum) const;
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// Used to generate a copy instruction based on the register class of
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// value.
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//
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MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
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int RegType) const;
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// The following 2 methods are used to order the instructions addeed by
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// the register allocator in association with function calling. See
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// SparcRegInfo.cpp for more details
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//
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void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
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MachineInstr *UnordInst,
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PhyRegAlloc &PRA) const;
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void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
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std::vector<MachineInstr *> &OrdVec,
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PhyRegAlloc &PRA) const;
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// Compute which register can be used for an argument, if any
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//
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int regNumForIntArg(bool inCallee, bool isVarArgsCall,
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unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
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unsigned& regClassId) const;
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int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
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unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
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unsigned& regClassId) const;
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public:
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UltraSparcRegInfo(const UltraSparc &tgt);
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// To find the register class used for a specified Type
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//
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unsigned getRegClassIDOfType(const Type *type,
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bool isCCReg = false) const;
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// To find the register class of a Value
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//
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inline unsigned getRegClassIDOfValue(const Value *Val,
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bool isCCReg = false) const {
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return getRegClassIDOfType(Val->getType(), isCCReg);
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}
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// To find the register class to which a specified register belongs
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//
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unsigned getRegClassIDOfReg(int unifiedRegNum) const;
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unsigned getRegClassIDOfRegType(int regType) const;
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// getZeroRegNum - returns the register that contains always zero this is the
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// unified register number
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//
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virtual int getZeroRegNum() const;
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// getCallAddressReg - returns the reg used for pushing the address when a
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// function is called. This can be used for other purposes between calls
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//
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unsigned getCallAddressReg() const;
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// Returns the register containing the return address.
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// It should be made sure that this register contains the return
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// value when a return instruction is reached.
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//
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unsigned getReturnAddressReg() const;
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// Number of registers used for passing int args (usually 6: %o0 - %o5)
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// and float args (usually 32: %f0 - %f31)
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//
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unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
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unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
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// The following methods are used to color special live ranges (e.g.
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// function args and return values etc.) with specific hardware registers
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// as required. See SparcRegInfo.cpp for the implementation for Sparc.
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//
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void suggestRegs4MethodArgs(const Function *Meth,
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LiveRangeInfo& LRI) const;
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void suggestRegs4CallArgs(MachineInstr *CallMI,
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LiveRangeInfo& LRI) const;
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void suggestReg4RetValue(MachineInstr *RetMI,
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LiveRangeInfo& LRI) const;
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void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
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AddedInstrns *FirstAI) const;
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void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
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AddedInstrns *CallAI, PhyRegAlloc &PRA,
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const BasicBlock *BB) const;
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void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
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AddedInstrns *RetAI) const;
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// method used for printing a register for debugging purposes
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//
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static void printReg(const LiveRange *LR);
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// Each register class has a seperate space for register IDs. To convert
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// a regId in a register class to a common Id, or vice versa,
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// we use the folloing methods.
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//
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// This method provides a unique number for each register
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inline int getUnifiedRegNum(unsigned regClassID, int reg) const {
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if (regClassID == IntRegClassID) {
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assert(reg < 32 && "Invalid reg. number");
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return reg;
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}
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else if (regClassID == FloatRegClassID) {
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assert(reg < 64 && "Invalid reg. number");
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return reg + 32; // we have 32 int regs
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}
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else if (regClassID == FloatCCRegClassID) {
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assert(reg < 4 && "Invalid reg. number");
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return reg + 32 + 64; // 32 int, 64 float
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}
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else if (regClassID == IntCCRegClassID ) {
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assert(reg == 0 && "Invalid reg. number");
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return reg + 4+ 32 + 64; // only one int CC reg
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}
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else if (reg==InvalidRegNum) {
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return InvalidRegNum;
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}
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else
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assert(0 && "Invalid register class");
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return 0;
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}
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// This method converts the unified number to the number in its class,
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// and returns the class ID in regClassID.
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inline int getClassRegNum(int ureg, unsigned& regClassID) const {
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if (ureg < 32) { regClassID = IntRegClassID; return ureg; }
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else if (ureg < 32+64) { regClassID = FloatRegClassID; return ureg-32; }
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else if (ureg < 4 +96) { regClassID = FloatCCRegClassID; return ureg-96; }
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else if (ureg < 1 +100) { regClassID = IntCCRegClassID; return ureg-100;}
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else if (ureg == InvalidRegNum) { return InvalidRegNum; }
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else { assert(0 && "Invalid unified register number"); }
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return 0;
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}
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// Returns the assembly-language name of the specified machine register.
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//
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virtual const char * const getUnifiedRegName(int reg) const;
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// returns the # of bytes of stack space allocated for each register
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// type. For Sparc, currently we allocate 8 bytes on stack for all
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// register types. We can optimize this later if necessary to save stack
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// space (However, should make sure that stack alignment is correct)
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//
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inline int getSpilledRegSize(int RegType) const {
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return 8;
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}
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// To obtain the return value and the indirect call address (if any)
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// contained in a CALL machine instruction
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//
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const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
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const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
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// The following methods are used to generate "copy" machine instructions
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// for an architecture.
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//
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// The function regTypeNeedsScratchReg() can be used to check whether a
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// scratch register is needed to copy a register of type `regType' to
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// or from memory. If so, such a scratch register can be provided by
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// the caller (e.g., if it knows which regsiters are free); otherwise
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// an arbitrary one will be chosen and spilled by the copy instructions.
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//
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bool regTypeNeedsScratchReg(int RegType,
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int& scratchRegClassId) const;
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void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
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unsigned SrcReg, unsigned DestReg,
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int RegType) const;
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void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
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unsigned SrcReg, unsigned DestPtrReg,
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int Offset, int RegType, int scratchReg = -1) const;
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void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
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unsigned SrcPtrReg, int Offset, unsigned DestReg,
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int RegType, int scratchReg = -1) const;
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void cpValue2Value(Value *Src, Value *Dest,
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std::vector<MachineInstr*>& mvec) const;
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// To see whether a register is a volatile (i.e., whehter it must be
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// preserved acorss calls)
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//
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inline bool isRegVolatile(int RegClassID, int Reg) const {
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return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
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}
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virtual unsigned getFramePointer() const;
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virtual unsigned getStackPointer() const;
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virtual int getInvalidRegNum() const {
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return InvalidRegNum;
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}
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// This method inserts the caller saving code for call instructions
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//
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void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
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std::vector<MachineInstr*>& instrnsAfter,
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MachineInstr *MInst,
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const BasicBlock *BB, PhyRegAlloc &PRA ) const;
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};
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//---------------------------------------------------------------------------
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// class UltraSparcSchedInfo
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//
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// Purpose:
|
|
// Interface to instruction scheduling information for UltraSPARC.
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// The parameter values above are based on UltraSPARC IIi.
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//---------------------------------------------------------------------------
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|
|
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class UltraSparcSchedInfo: public MachineSchedInfo {
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public:
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UltraSparcSchedInfo(const TargetMachine &tgt);
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protected:
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virtual void initializeResources();
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};
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|
|
|
|
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//---------------------------------------------------------------------------
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|
// class UltraSparcFrameInfo
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|
//
|
|
// Purpose:
|
|
// Interface to stack frame layout info for the UltraSPARC.
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|
// Starting offsets for each area of the stack frame are aligned at
|
|
// a multiple of getStackFrameSizeAlignment().
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|
//---------------------------------------------------------------------------
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|
|
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class UltraSparcFrameInfo: public MachineFrameInfo {
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public:
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UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
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|
|
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public:
|
|
// These methods provide constant parameters of the frame layout.
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|
//
|
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int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
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int getMinStackFrameSize() const { return MinStackFrameSize; }
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int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
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int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
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|
bool argsOnStackHaveFixedSize() const { return true; }
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|
|
|
// This method adjusts a stack offset to meet alignment rules of target.
|
|
// The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
|
|
virtual int adjustAlignment (int unalignedOffset,
|
|
bool growUp,
|
|
unsigned int align) const {
|
|
return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
|
|
}
|
|
|
|
// These methods compute offsets using the frame contents for a
|
|
// particular function. The frame contents are obtained from the
|
|
// MachineCodeInfoForMethod object for the given function.
|
|
//
|
|
int getFirstIncomingArgOffset (MachineFunction& mcInfo,
|
|
bool& growUp) const
|
|
{
|
|
growUp = true; // arguments area grows upwards
|
|
return FirstIncomingArgOffsetFromFP;
|
|
}
|
|
int getFirstOutgoingArgOffset (MachineFunction& mcInfo,
|
|
bool& growUp) const
|
|
{
|
|
growUp = true; // arguments area grows upwards
|
|
return FirstOutgoingArgOffsetFromSP;
|
|
}
|
|
int getFirstOptionalOutgoingArgOffset(MachineFunction& mcInfo,
|
|
bool& growUp)const
|
|
{
|
|
growUp = true; // arguments area grows upwards
|
|
return FirstOptionalOutgoingArgOffsetFromSP;
|
|
}
|
|
|
|
int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
|
|
bool& growUp) const;
|
|
int getRegSpillAreaOffset (MachineFunction& mcInfo,
|
|
bool& growUp) const;
|
|
int getTmpAreaOffset (MachineFunction& mcInfo,
|
|
bool& growUp) const;
|
|
int getDynamicAreaOffset (MachineFunction& mcInfo,
|
|
bool& growUp) const;
|
|
|
|
//
|
|
// These methods specify the base register used for each stack area
|
|
// (generally FP or SP)
|
|
//
|
|
virtual int getIncomingArgBaseRegNum() const {
|
|
return (int) target.getRegInfo().getFramePointer();
|
|
}
|
|
virtual int getOutgoingArgBaseRegNum() const {
|
|
return (int) target.getRegInfo().getStackPointer();
|
|
}
|
|
virtual int getOptionalOutgoingArgBaseRegNum() const {
|
|
return (int) target.getRegInfo().getStackPointer();
|
|
}
|
|
virtual int getAutomaticVarBaseRegNum() const {
|
|
return (int) target.getRegInfo().getFramePointer();
|
|
}
|
|
virtual int getRegSpillAreaBaseRegNum() const {
|
|
return (int) target.getRegInfo().getFramePointer();
|
|
}
|
|
virtual int getDynamicAreaBaseRegNum() const {
|
|
return (int) target.getRegInfo().getStackPointer();
|
|
}
|
|
|
|
private:
|
|
/*----------------------------------------------------------------------
|
|
This diagram shows the stack frame layout used by llc on Sparc V9.
|
|
Note that only the location of automatic variables, spill area,
|
|
temporary storage, and dynamically allocated stack area are chosen
|
|
by us. The rest conform to the Sparc V9 ABI.
|
|
All stack addresses are offset by OFFSET = 0x7ff (2047).
|
|
|
|
Alignment assumpteions and other invariants:
|
|
(1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
|
|
(2) Variables in automatic, spill, temporary, or dynamic regions
|
|
are aligned according to their size as in all memory accesses.
|
|
(3) Everything below the dynamically allocated stack area is only used
|
|
during a call to another function, so it is never needed when
|
|
the current function is active. This is why space can be allocated
|
|
dynamically by incrementing %sp any time within the function.
|
|
|
|
STACK FRAME LAYOUT:
|
|
|
|
...
|
|
%fp+OFFSET+176 Optional extra incoming arguments# 1..N
|
|
%fp+OFFSET+168 Incoming argument #6
|
|
... ...
|
|
%fp+OFFSET+128 Incoming argument #1
|
|
... ...
|
|
---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
|
|
%fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
|
|
Spill area
|
|
Temporary storage
|
|
...
|
|
|
|
%sp+OFFSET+176+8N Bottom of dynamically allocated stack area
|
|
%sp+OFFSET+168+8N Optional extra outgoing argument# N
|
|
... ...
|
|
%sp+OFFSET+176 Optional extra outgoing argument# 1
|
|
%sp+OFFSET+168 Outgoing argument #6
|
|
... ...
|
|
%sp+OFFSET+128 Outgoing argument #1
|
|
%sp+OFFSET+120 Save area for %i7
|
|
... ...
|
|
%sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
|
|
|
|
*----------------------------------------------------------------------*/
|
|
|
|
// All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
|
|
static const int OFFSET = (int) 0x7ff;
|
|
static const int StackFrameSizeAlignment = 16;
|
|
static const int MinStackFrameSize = 176;
|
|
static const int NumFixedOutgoingArgs = 6;
|
|
static const int SizeOfEachArgOnStack = 8;
|
|
static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
|
|
static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
|
|
static const int StaticAreaOffsetFromFP = 0 + OFFSET;
|
|
static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
|
|
static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
|
|
};
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// class UltraSparcCacheInfo
|
|
//
|
|
// Purpose:
|
|
// Interface to cache parameters for the UltraSPARC.
|
|
// Just use defaults for now.
|
|
//---------------------------------------------------------------------------
|
|
|
|
class UltraSparcCacheInfo: public MachineCacheInfo {
|
|
public:
|
|
UltraSparcCacheInfo(const TargetMachine &T) : MachineCacheInfo(T) {}
|
|
};
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// class UltraSparcOptInfo
|
|
//
|
|
// Purpose:
|
|
// Interface to machine-level optimization routines for the UltraSPARC.
|
|
//---------------------------------------------------------------------------
|
|
|
|
class UltraSparcOptInfo: public MachineOptInfo {
|
|
public:
|
|
UltraSparcOptInfo(const TargetMachine &T) : MachineOptInfo(T) {}
|
|
|
|
virtual bool IsUselessCopy (const MachineInstr* MI) const;
|
|
};
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// class UltraSparcMachine
|
|
//
|
|
// Purpose:
|
|
// Primary interface to machine description for the UltraSPARC.
|
|
// Primarily just initializes machine-dependent parameters in
|
|
// class TargetMachine, and creates machine-dependent subclasses
|
|
// for classes such as InstrInfo, SchedInfo and RegInfo.
|
|
//---------------------------------------------------------------------------
|
|
|
|
class UltraSparc : public TargetMachine {
|
|
UltraSparcInstrInfo instrInfo;
|
|
UltraSparcSchedInfo schedInfo;
|
|
UltraSparcRegInfo regInfo;
|
|
UltraSparcFrameInfo frameInfo;
|
|
UltraSparcCacheInfo cacheInfo;
|
|
UltraSparcOptInfo optInfo;
|
|
public:
|
|
UltraSparc();
|
|
|
|
virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
|
|
virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
|
|
virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
|
|
virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
|
|
virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
|
|
virtual const MachineOptInfo &getOptInfo() const { return optInfo; }
|
|
|
|
virtual void addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
|
|
|
|
// getPrologEpilogCodeInserter - Inserts prolog/epilog code.
|
|
virtual Pass* getPrologEpilogInsertionPass();
|
|
|
|
// getFunctionAsmPrinterPass - Writes out machine code for a single function
|
|
virtual Pass* getFunctionAsmPrinterPass(std::ostream &Out);
|
|
|
|
// getModuleAsmPrinterPass - Writes generated machine code to assembly file.
|
|
virtual Pass* getModuleAsmPrinterPass(std::ostream &Out);
|
|
|
|
// getEmitBytecodeToAsmPass - Emits final LLVM bytecode to assembly file.
|
|
virtual Pass* getEmitBytecodeToAsmPass(std::ostream &Out);
|
|
};
|
|
|
|
#endif
|