mirror of
https://github.com/c64scene-ar/llvm-6502.git
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86050dc8cc
- This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
43 lines
876 B
LLVM
43 lines
876 B
LLVM
; RUN: llc < %s -march=arm | FileCheck %s
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define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
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; CHECK: t1:
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; CHECK: bxlt lr
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%tmp2 = icmp sgt i32 %c, 10
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%tmp5 = icmp slt i32 %d, 4
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%tmp8 = or i1 %tmp5, %tmp2
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%tmp13 = add i32 %b, %a
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br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
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cond_true:
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%tmp15 = add i32 %tmp13, %c
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%tmp1821 = sub i32 %tmp15, %d
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ret i32 %tmp1821
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UnifiedReturnBlock:
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ret i32 %tmp13
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}
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define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) {
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; CHECK: t2:
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; CHECK: bxgt lr
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; CHECK: cmp
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; CHECK: addge
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; CHECK: subge
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; CHECK-NOT: bxge lr
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; CHECK: bx lr
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%tmp2 = icmp sgt i32 %c, 10
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%tmp5 = icmp slt i32 %d, 4
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%tmp8 = and i1 %tmp5, %tmp2
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%tmp13 = add i32 %b, %a
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br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
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cond_true:
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%tmp15 = add i32 %tmp13, %c
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%tmp1821 = sub i32 %tmp15, %d
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ret i32 %tmp1821
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UnifiedReturnBlock:
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ret i32 %tmp13
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}
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