mirror of
https://github.com/c64scene-ar/llvm-6502.git
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13a949071c
1. A delay slot filler that searches for valid instructions
to fill the delay slot with. Previously NOPs would always
be inserted into delay slots.
2. Support for MC based instruction printer added.
3. Support for MC based machine code generation and ELF
file generation. ELF file generation does not yet
completely work as much of the ELF support infrastructure
is still x86/x86-64 specific.
4. General clean up of the MBlaze backend code. Much of the
tablegen code has been cleanup and simplified.
Bug Fixes:
1. Removed duplicate periods from subtarget feature descriptions.
2. Many of the instructions had bad machine code information
in the tablegen files. Much of this has been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116986 91177308-0d34-0410-b5e6-96231b3b80d8
267 lines
8.5 KiB
LLVM
267 lines
8.5 KiB
LLVM
; Test some of the calling convention lowering done by the MBlaze backend.
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; We test that integer values are passed in the correct registers and
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; returned in the correct registers. Additionally, we test that the stack
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; is used as appropriate for passing arguments that cannot be placed into
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; registers.
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;
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; RUN: llc < %s -march=mblaze | FileCheck %s
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declare i32 @printf(i8*, ...)
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@MSG = internal constant [13 x i8] c"Message: %d\0A\00"
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define void @params0_noret() {
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; CHECK: params0_noret:
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ret void
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; CHECK-NOT: {{.* r3, .*, .*}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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}
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define i8 @params0_8bitret() {
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; CHECK: params0_8bitret:
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ret i8 1
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; CHECK-NOT: {{.* r3, .*, .*}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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; CHECK: {{.* r3, r0, 1}}
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}
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define i16 @params0_16bitret() {
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; CHECK: params0_16bitret:
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ret i16 1
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; CHECK: rtsd
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; CHECK: {{.* r3, r0, 1}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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}
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define i32 @params0_32bitret() {
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; CHECK: params0_32bitret:
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ret i32 1
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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; CHECK: {{.* r3, r0, 1}}
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}
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define i64 @params0_64bitret() {
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; CHECK: params0_64bitret:
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ret i64 1
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; CHECK: {{.* r3, r0, .*}}
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; CHECK: rtsd
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; CHECK: {{.* r4, r0, 1}}
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}
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define i32 @params1_32bitret(i32 %a) {
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; CHECK: params1_32bitret:
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ret i32 %a
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; CHECK-NOT: {{.* r3, .*, .*}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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; CHECK: {{.* r3, r5, r0}}
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}
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define i32 @params2_32bitret(i32 %a, i32 %b) {
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; CHECK: params2_32bitret:
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ret i32 %b
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; CHECK-NOT: {{.* r3, .*, .*}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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; CHECK: {{.* r3, r6, r0}}
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}
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define i32 @params3_32bitret(i32 %a, i32 %b, i32 %c) {
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; CHECK: params3_32bitret:
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ret i32 %c
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; CHECK-NOT: {{.* r3, .*, .*}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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; CHECK: {{.* r3, r7, r0}}
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}
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define i32 @params4_32bitret(i32 %a, i32 %b, i32 %c, i32 %d) {
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; CHECK: params4_32bitret:
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ret i32 %d
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; CHECK-NOT: {{.* r3, .*, .*}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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; CHECK: {{.* r3, r8, r0}}
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}
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define i32 @params5_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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; CHECK: params5_32bitret:
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ret i32 %e
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; CHECK-NOT: {{.* r3, .*, .*}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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; CHECK: {{.* r3, r9, r0}}
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}
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define i32 @params6_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) {
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; CHECK: params6_32bitret:
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ret i32 %f
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; CHECK-NOT: {{.* r3, .*, .*}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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; CHECK: {{.* r3, r10, r0}}
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}
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define i32 @params7_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
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i32 %g) {
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; CHECK: params7_32bitret:
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ret i32 %g
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; CHECK: {{lwi? r3, r1, 32}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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}
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define i32 @params8_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
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i32 %g, i32 %h) {
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; CHECK: params8_32bitret:
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ret i32 %h
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; CHECK: {{lwi? r3, r1, 36}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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}
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define i32 @params9_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
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i32 %g, i32 %h, i32 %i) {
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; CHECK: params9_32bitret:
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ret i32 %i
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; CHECK: {{lwi? r3, r1, 40}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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}
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define i32 @params10_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
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i32 %g, i32 %h, i32 %i, i32 %j) {
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; CHECK: params10_32bitret:
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ret i32 %j
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; CHECK: {{lwi? r3, r1, 44}}
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; CHECK-NOT: {{.* r4, .*, .*}}
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; CHECK: rtsd
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}
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define void @testing() {
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%MSG.1 = getelementptr [13 x i8]* @MSG, i32 0, i32 0
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call void @params0_noret()
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; CHECK: brlid
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%tmp.1 = call i8 @params0_8bitret()
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i8 %tmp.1)
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%tmp.2 = call i16 @params0_16bitret()
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i16 %tmp.2)
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%tmp.3 = call i32 @params0_32bitret()
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.3)
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%tmp.4 = call i64 @params0_64bitret()
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i64 %tmp.4)
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%tmp.5 = call i32 @params1_32bitret(i32 1)
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; CHECK: {{.* r5, .*, .*}}
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.5)
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%tmp.6 = call i32 @params2_32bitret(i32 1, i32 2)
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; CHECK: {{.* r5, .*, .*}}
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; CHECK: {{.* r6, .*, .*}}
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.6)
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%tmp.7 = call i32 @params3_32bitret(i32 1, i32 2, i32 3)
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; CHECK: {{.* r5, .*, .*}}
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; CHECK: {{.* r6, .*, .*}}
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; CHECK: {{.* r7, .*, .*}}
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.7)
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%tmp.8 = call i32 @params4_32bitret(i32 1, i32 2, i32 3, i32 4)
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; CHECK: {{.* r5, .*, .*}}
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; CHECK: {{.* r6, .*, .*}}
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; CHECK: {{.* r7, .*, .*}}
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; CHECK: {{.* r8, .*, .*}}
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.8)
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%tmp.9 = call i32 @params5_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5)
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; CHECK: {{.* r5, .*, .*}}
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; CHECK: {{.* r6, .*, .*}}
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; CHECK: {{.* r7, .*, .*}}
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; CHECK: {{.* r8, .*, .*}}
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; CHECK: {{.* r9, .*, .*}}
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.9)
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%tmp.10 = call i32 @params6_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
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i32 6)
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; CHECK: {{.* r5, .*, .*}}
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; CHECK: {{.* r6, .*, .*}}
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; CHECK: {{.* r7, .*, .*}}
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; CHECK: {{.* r8, .*, .*}}
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; CHECK: {{.* r9, .*, .*}}
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; CHECK: {{.* r10, .*, .*}}
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.10)
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%tmp.11 = call i32 @params7_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
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i32 6, i32 7)
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; CHECK: {{swi? .*, r1, 28}}
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; CHECK: {{.* r5, .*, .*}}
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; CHECK: {{.* r6, .*, .*}}
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; CHECK: {{.* r7, .*, .*}}
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; CHECK: {{.* r8, .*, .*}}
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; CHECK: {{.* r9, .*, .*}}
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; CHECK: {{.* r10, .*, .*}}
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.11)
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%tmp.12 = call i32 @params8_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
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i32 6, i32 7, i32 8)
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; CHECK: {{swi? .*, r1, 28}}
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; CHECK: {{swi? .*, r1, 32}}
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; CHECK: {{.* r5, .*, .*}}
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; CHECK: {{.* r6, .*, .*}}
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; CHECK: {{.* r7, .*, .*}}
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; CHECK: {{.* r8, .*, .*}}
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; CHECK: {{.* r9, .*, .*}}
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; CHECK: {{.* r10, .*, .*}}
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.12)
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%tmp.13 = call i32 @params9_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
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i32 6, i32 7, i32 8, i32 9)
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; CHECK: {{swi? .*, r1, 28}}
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; CHECK: {{swi? .*, r1, 32}}
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; CHECK: {{swi? .*, r1, 36}}
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; CHECK: {{.* r5, .*, .*}}
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; CHECK: {{.* r6, .*, .*}}
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; CHECK: {{.* r7, .*, .*}}
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; CHECK: {{.* r8, .*, .*}}
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; CHECK: {{.* r9, .*, .*}}
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; CHECK: {{.* r10, .*, .*}}
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.13)
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%tmp.14 = call i32 @params10_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
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i32 6, i32 7, i32 8, i32 9, i32 10)
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; CHECK: {{swi? .*, r1, 28}}
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; CHECK: {{swi? .*, r1, 32}}
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; CHECK: {{swi? .*, r1, 36}}
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; CHECK: {{swi? .*, r1, 40}}
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; CHECK: {{.* r5, .*, .*}}
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; CHECK: {{.* r6, .*, .*}}
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; CHECK: {{.* r7, .*, .*}}
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; CHECK: {{.* r8, .*, .*}}
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; CHECK: {{.* r9, .*, .*}}
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; CHECK: {{.* r10, .*, .*}}
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; CHECK: brlid
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call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.14)
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ret void
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}
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