mirror of
https://github.com/c64scene-ar/llvm-6502.git
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13a949071c
1. A delay slot filler that searches for valid instructions
to fill the delay slot with. Previously NOPs would always
be inserted into delay slots.
2. Support for MC based instruction printer added.
3. Support for MC based machine code generation and ELF
file generation. ELF file generation does not yet
completely work as much of the ELF support infrastructure
is still x86/x86-64 specific.
4. General clean up of the MBlaze backend code. Much of the
tablegen code has been cleanup and simplified.
Bug Fixes:
1. Removed duplicate periods from subtarget feature descriptions.
2. Many of the instructions had bad machine code information
in the tablegen files. Much of this has been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116986 91177308-0d34-0410-b5e6-96231b3b80d8
118 lines
2.5 KiB
LLVM
118 lines
2.5 KiB
LLVM
; Ensure that shifts are lowered to loops when the barrel shifter unit is
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; not available in the hardware and that loops are not used when the
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; barrel shifter unit is available in the hardware.
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;
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; RUN: llc < %s -march=mblaze | FileCheck -check-prefix=FUN %s
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; RUN: llc < %s -march=mblaze -mattr=+barrel | FileCheck -check-prefix=SHT %s
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define i8 @test_i8(i8 %a, i8 %b) {
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; FUN: test_i8:
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; SHT: test_i8:
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%tmp.1 = shl i8 %a, %b
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; FUN: andi
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; FUN: add
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; FUN: bnei
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; SHT-NOT: andi
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; SHT-NOT: bnei
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ret i8 %tmp.1
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; FUN: rtsd
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; SHT: rtsd
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; FUN-NOT: bsll
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; SHT-NEXT: bsll
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}
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define i8 @testc_i8(i8 %a, i8 %b) {
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; FUN: testc_i8:
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; SHT: testc_i8:
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%tmp.1 = shl i8 %a, 5
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; FUN: andi
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; FUN: add
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; FUN: bnei
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; SHT-NOT: andi
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; SHT-NOT: add
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; SHT-NOT: bnei
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ret i8 %tmp.1
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; FUN: rtsd
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; SHT: rtsd
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; FUN-NOT: bsll
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; SHT-NEXT: bslli
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}
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define i16 @test_i16(i16 %a, i16 %b) {
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; FUN: test_i16:
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; SHT: test_i16:
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%tmp.1 = shl i16 %a, %b
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; FUN: andi
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; FUN: add
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; FUN: bnei
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; SHT-NOT: andi
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; SHT-NOT: bnei
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ret i16 %tmp.1
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; FUN: rtsd
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; SHT: rtsd
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; FUN-NOT: bsll
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; SHT-NEXT: bsll
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}
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define i16 @testc_i16(i16 %a, i16 %b) {
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; FUN: testc_i16:
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; SHT: testc_i16:
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%tmp.1 = shl i16 %a, 5
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; FUN: andi
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; FUN: add
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; FUN: bnei
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; SHT-NOT: andi
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; SHT-NOT: add
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; SHT-NOT: bnei
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ret i16 %tmp.1
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; FUN: rtsd
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; SHT: rtsd
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; FUN-NOT: bsll
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; SHT-NEXT: bslli
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}
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define i32 @test_i32(i32 %a, i32 %b) {
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; FUN: test_i32:
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; SHT: test_i32:
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%tmp.1 = shl i32 %a, %b
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; FUN: andi
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; FUN: add
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; FUN: bnei
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; SHT-NOT: andi
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; SHT-NOT: bnei
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ret i32 %tmp.1
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; FUN: rtsd
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; SHT: rtsd
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; FUN-NOT: bsll
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; SHT-NEXT: bsll
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}
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define i32 @testc_i32(i32 %a, i32 %b) {
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; FUN: testc_i32:
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; SHT: testc_i32:
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%tmp.1 = shl i32 %a, 5
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; FUN: andi
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; FUN: add
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; FUN: bnei
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; SHT-NOT: andi
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; SHT-NOT: add
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; SHT-NOT: bnei
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ret i32 %tmp.1
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; FUN: rtsd
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; SHT: rtsd
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; FUN-NOT: bsll
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; SHT-NEXT: bslli
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}
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