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https://github.com/c64scene-ar/llvm-6502.git
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674be02d52
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172025 91177308-0d34-0410-b5e6-96231b3b80d8
143 lines
4.3 KiB
C++
143 lines
4.3 KiB
C++
//===----- ResourcePriorityQueue.h - A DFA-oriented priority queue -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ResourcePriorityQueue class, which is a
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// SchedulingPriorityQueue that schedules using DFA state to
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// reduce the length of the critical path through the basic block
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// on VLIW platforms.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_RESOURCEPRIORITYQUEUE_H
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#define LLVM_CODEGEN_RESOURCEPRIORITYQUEUE_H
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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namespace llvm {
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class ResourcePriorityQueue;
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/// Sorting functions for the Available queue.
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struct resource_sort : public std::binary_function<SUnit*, SUnit*, bool> {
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ResourcePriorityQueue *PQ;
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explicit resource_sort(ResourcePriorityQueue *pq) : PQ(pq) {}
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bool operator()(const SUnit* left, const SUnit* right) const;
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};
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class ResourcePriorityQueue : public SchedulingPriorityQueue {
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/// SUnits - The SUnits for the current graph.
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std::vector<SUnit> *SUnits;
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/// NumNodesSolelyBlocking - This vector contains, for every node in the
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/// Queue, the number of nodes that the node is the sole unscheduled
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/// predecessor for. This is used as a tie-breaker heuristic for better
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/// mobility.
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std::vector<unsigned> NumNodesSolelyBlocking;
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/// Queue - The queue.
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std::vector<SUnit*> Queue;
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/// RegPressure - Tracking current reg pressure per register class.
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///
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std::vector<unsigned> RegPressure;
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/// RegLimit - Tracking the number of allocatable registers per register
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/// class.
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std::vector<unsigned> RegLimit;
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resource_sort Picker;
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const TargetRegisterInfo *TRI;
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const TargetLowering *TLI;
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const TargetInstrInfo *TII;
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const InstrItineraryData* InstrItins;
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/// ResourcesModel - Represents VLIW state.
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/// Not limited to VLIW targets per say, but assumes
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/// definition of DFA by a target.
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DFAPacketizer *ResourcesModel;
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/// Resource model - packet/bundle model. Purely
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/// internal at the time.
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std::vector<SUnit*> Packet;
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/// Heuristics for estimating register pressure.
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unsigned ParallelLiveRanges;
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signed HorizontalVerticalBalance;
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public:
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ResourcePriorityQueue(SelectionDAGISel *IS);
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~ResourcePriorityQueue() {
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delete ResourcesModel;
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}
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bool isBottomUp() const { return false; }
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void initNodes(std::vector<SUnit> &sunits);
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void addNode(const SUnit *SU) {
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NumNodesSolelyBlocking.resize(SUnits->size(), 0);
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}
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void updateNode(const SUnit *SU) {}
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void releaseState() {
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SUnits = 0;
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}
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unsigned getLatency(unsigned NodeNum) const {
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assert(NodeNum < (*SUnits).size());
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return (*SUnits)[NodeNum].getHeight();
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}
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unsigned getNumSolelyBlockNodes(unsigned NodeNum) const {
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assert(NodeNum < NumNodesSolelyBlocking.size());
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return NumNodesSolelyBlocking[NodeNum];
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}
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/// Single cost function reflecting benefit of scheduling SU
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/// in the current cycle.
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signed SUSchedulingCost (SUnit *SU);
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/// InitNumRegDefsLeft - Determine the # of regs defined by this node.
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///
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void initNumRegDefsLeft(SUnit *SU);
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void updateNumRegDefsLeft(SUnit *SU);
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signed regPressureDelta(SUnit *SU, bool RawPressure = false);
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signed rawRegPressureDelta (SUnit *SU, unsigned RCId);
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bool empty() const { return Queue.empty(); }
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virtual void push(SUnit *U);
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virtual SUnit *pop();
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virtual void remove(SUnit *SU);
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virtual void dump(ScheduleDAG* DAG) const;
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/// scheduledNode - Main resource tracking point.
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void scheduledNode(SUnit *Node);
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bool isResourceAvailable(SUnit *SU);
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void reserveResources(SUnit *SU);
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private:
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void adjustPriorityOfUnscheduledPreds(SUnit *SU);
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SUnit *getSingleUnscheduledPred(SUnit *SU);
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unsigned numberRCValPredInSU (SUnit *SU, unsigned RCId);
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unsigned numberRCValSuccInSU (SUnit *SU, unsigned RCId);
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};
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}
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#endif
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