mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 23:29:22 +00:00
Many targets use pseudo instructions to help register allocation. Like the COPY instruction, these pseudos can be expanded after register allocation. The early expansion can make life easier for PEI and the post-ra scheduler. This patch adds a hook that is called for all remaining pseudo instructions from the ExpandPostRAPseudos pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8
230 lines
7.5 KiB
C++
230 lines
7.5 KiB
C++
//===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
|
|
// instructions after register allocation.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#define DEBUG_TYPE "postrapseudos"
|
|
#include "llvm/CodeGen/Passes.h"
|
|
#include "llvm/Function.h"
|
|
#include "llvm/CodeGen/MachineFunctionPass.h"
|
|
#include "llvm/CodeGen/MachineInstr.h"
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
|
#include "llvm/Target/TargetMachine.h"
|
|
#include "llvm/Support/Debug.h"
|
|
#include "llvm/Support/raw_ostream.h"
|
|
using namespace llvm;
|
|
|
|
namespace {
|
|
struct ExpandPostRA : public MachineFunctionPass {
|
|
private:
|
|
const TargetRegisterInfo *TRI;
|
|
const TargetInstrInfo *TII;
|
|
|
|
public:
|
|
static char ID; // Pass identification, replacement for typeid
|
|
ExpandPostRA() : MachineFunctionPass(ID) {}
|
|
|
|
const char *getPassName() const {
|
|
return "Post-RA pseudo instruction expansion pass";
|
|
}
|
|
|
|
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
|
|
AU.setPreservesCFG();
|
|
AU.addPreservedID(MachineLoopInfoID);
|
|
AU.addPreservedID(MachineDominatorsID);
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
|
|
/// runOnMachineFunction - pass entry point
|
|
bool runOnMachineFunction(MachineFunction&);
|
|
|
|
private:
|
|
bool LowerSubregToReg(MachineInstr *MI);
|
|
bool LowerCopy(MachineInstr *MI);
|
|
|
|
void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
|
|
const TargetRegisterInfo *TRI);
|
|
void TransferImplicitDefs(MachineInstr *MI);
|
|
};
|
|
} // end anonymous namespace
|
|
|
|
char ExpandPostRA::ID = 0;
|
|
|
|
FunctionPass *llvm::createExpandPostRAPseudosPass() {
|
|
return new ExpandPostRA();
|
|
}
|
|
|
|
/// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
|
|
/// and the lowered replacement instructions immediately precede it.
|
|
/// Mark the replacement instructions with the dead flag.
|
|
void
|
|
ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
|
|
const TargetRegisterInfo *TRI) {
|
|
for (MachineBasicBlock::iterator MII =
|
|
prior(MachineBasicBlock::iterator(MI)); ; --MII) {
|
|
if (MII->addRegisterDead(DstReg, TRI))
|
|
break;
|
|
assert(MII != MI->getParent()->begin() &&
|
|
"copyPhysReg output doesn't reference destination register!");
|
|
}
|
|
}
|
|
|
|
/// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
|
|
/// replacement instructions immediately precede it. Copy any implicit-def
|
|
/// operands from MI to the replacement instruction.
|
|
void
|
|
ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) {
|
|
MachineBasicBlock::iterator CopyMI = MI;
|
|
--CopyMI;
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
|
|
continue;
|
|
CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
|
|
}
|
|
}
|
|
|
|
bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
|
|
MI->getOperand(1).isImm() &&
|
|
(MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
|
|
MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
|
|
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
unsigned InsReg = MI->getOperand(2).getReg();
|
|
assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
|
|
unsigned SubIdx = MI->getOperand(3).getImm();
|
|
|
|
assert(SubIdx != 0 && "Invalid index for insert_subreg");
|
|
unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
|
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
|
|
"Insert destination must be in a physical register");
|
|
assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
|
|
"Inserted value must be in a physical register");
|
|
|
|
DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
|
|
|
|
if (DstSubReg == InsReg) {
|
|
// No need to insert an identify copy instruction.
|
|
// Watch out for case like this:
|
|
// %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
|
|
// We must leave %RAX live.
|
|
if (DstReg != InsReg) {
|
|
MI->setDesc(TII->get(TargetOpcode::KILL));
|
|
MI->RemoveOperand(3); // SubIdx
|
|
MI->RemoveOperand(1); // Imm
|
|
DEBUG(dbgs() << "subreg: replace by: " << *MI);
|
|
return true;
|
|
}
|
|
DEBUG(dbgs() << "subreg: eliminated!");
|
|
} else {
|
|
TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
|
|
MI->getOperand(2).isKill());
|
|
// Transfer the kill/dead flags, if needed.
|
|
if (MI->getOperand(0).isDead())
|
|
TransferDeadFlag(MI, DstSubReg, TRI);
|
|
DEBUG({
|
|
MachineBasicBlock::iterator dMI = MI;
|
|
dbgs() << "subreg: " << *(--dMI);
|
|
});
|
|
}
|
|
|
|
DEBUG(dbgs() << '\n');
|
|
MBB->erase(MI);
|
|
return true;
|
|
}
|
|
|
|
bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
|
|
MachineOperand &DstMO = MI->getOperand(0);
|
|
MachineOperand &SrcMO = MI->getOperand(1);
|
|
|
|
if (SrcMO.getReg() == DstMO.getReg()) {
|
|
DEBUG(dbgs() << "identity copy: " << *MI);
|
|
// No need to insert an identity copy instruction, but replace with a KILL
|
|
// if liveness is changed.
|
|
if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
|
|
// We must make sure the super-register gets killed. Replace the
|
|
// instruction with KILL.
|
|
MI->setDesc(TII->get(TargetOpcode::KILL));
|
|
DEBUG(dbgs() << "replaced by: " << *MI);
|
|
return true;
|
|
}
|
|
// Vanilla identity copy.
|
|
MI->eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
DEBUG(dbgs() << "real copy: " << *MI);
|
|
TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
|
|
DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
|
|
|
|
if (DstMO.isDead())
|
|
TransferDeadFlag(MI, DstMO.getReg(), TRI);
|
|
if (MI->getNumOperands() > 2)
|
|
TransferImplicitDefs(MI);
|
|
DEBUG({
|
|
MachineBasicBlock::iterator dMI = MI;
|
|
dbgs() << "replaced by: " << *(--dMI);
|
|
});
|
|
MI->eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
/// runOnMachineFunction - Reduce subregister inserts and extracts to register
|
|
/// copies.
|
|
///
|
|
bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
|
|
DEBUG(dbgs() << "Machine Function\n"
|
|
<< "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
|
|
<< "********** Function: "
|
|
<< MF.getFunction()->getName() << '\n');
|
|
TRI = MF.getTarget().getRegisterInfo();
|
|
TII = MF.getTarget().getInstrInfo();
|
|
|
|
bool MadeChange = false;
|
|
|
|
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
|
|
mbbi != mbbe; ++mbbi) {
|
|
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
|
|
mi != me;) {
|
|
MachineInstr *MI = mi;
|
|
// Advance iterator here because MI may be erased.
|
|
++mi;
|
|
switch (MI->getOpcode()) {
|
|
case TargetOpcode::SUBREG_TO_REG:
|
|
MadeChange |= LowerSubregToReg(MI);
|
|
break;
|
|
case TargetOpcode::COPY:
|
|
MadeChange |= LowerCopy(MI);
|
|
break;
|
|
case TargetOpcode::DBG_VALUE:
|
|
continue;
|
|
case TargetOpcode::INSERT_SUBREG:
|
|
case TargetOpcode::EXTRACT_SUBREG:
|
|
llvm_unreachable("Sub-register pseudos should have been eliminated.");
|
|
default:
|
|
if (MI->getDesc().isPseudo())
|
|
MadeChange |= TII->expandPostRAPseudo(MI);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
return MadeChange;
|
|
}
|