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https://github.com/c64scene-ar/llvm-6502.git
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d99338105b
This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195890 91177308-0d34-0410-b5e6-96231b3b80d8
110 lines
5.8 KiB
TableGen
110 lines
5.8 KiB
TableGen
//===-- PPCScheduleG5.td - PPC G5 Scheduling Definitions ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the G5 (970) processor.
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//
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//===----------------------------------------------------------------------===//
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def G5Itineraries : ProcessorItineraries<
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[IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [], [
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InstrItinData<IIC_IntSimple , [InstrStage<2, [IU1, IU2]>]>,
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InstrItinData<IIC_IntGeneral , [InstrStage<2, [IU1, IU2]>]>,
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InstrItinData<IIC_IntCompare , [InstrStage<3, [IU1, IU2]>]>,
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InstrItinData<IIC_IntDivD , [InstrStage<68, [IU1]>]>,
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InstrItinData<IIC_IntDivW , [InstrStage<36, [IU1]>]>,
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InstrItinData<IIC_IntMFFS , [InstrStage<6, [IU2]>]>,
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InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [VFPU]>]>,
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InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [FPU1, FPU2]>]>,
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InstrItinData<IIC_IntMulHD , [InstrStage<7, [IU1, IU2]>]>,
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InstrItinData<IIC_IntMulHW , [InstrStage<5, [IU1, IU2]>]>,
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InstrItinData<IIC_IntMulHWU , [InstrStage<5, [IU1, IU2]>]>,
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InstrItinData<IIC_IntMulLI , [InstrStage<4, [IU1, IU2]>]>,
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InstrItinData<IIC_IntRFID , [InstrStage<1, [IU2]>]>,
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InstrItinData<IIC_IntRotateD , [InstrStage<2, [IU1, IU2]>]>,
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InstrItinData<IIC_IntRotateDI , [InstrStage<2, [IU1, IU2]>]>,
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InstrItinData<IIC_IntRotate , [InstrStage<4, [IU1, IU2]>]>,
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InstrItinData<IIC_IntShift , [InstrStage<2, [IU1, IU2]>]>,
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InstrItinData<IIC_IntTrapD , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<IIC_IntTrapW , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<IIC_BrB , [InstrStage<1, [BPU]>]>,
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InstrItinData<IIC_BrCR , [InstrStage<4, [BPU]>]>,
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InstrItinData<IIC_BrMCR , [InstrStage<2, [BPU]>]>,
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InstrItinData<IIC_BrMCRX , [InstrStage<3, [BPU]>]>,
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InstrItinData<IIC_LdStDCBF , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLoad , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStStore , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStDSS , [InstrStage<10, [SLU]>]>,
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InstrItinData<IIC_LdStICBI , [InstrStage<40, [SLU]>]>,
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InstrItinData<IIC_LdStSTFD , [InstrStage<4, [SLU]>]>,
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InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [SLU]>]>,
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InstrItinData<IIC_LdStLD , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLDU , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLDARX , [InstrStage<11, [SLU]>]>,
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InstrItinData<IIC_LdStLFD , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLFDU , [InstrStage<5, [SLU]>]>,
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InstrItinData<IIC_LdStLHA , [InstrStage<5, [SLU]>]>,
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InstrItinData<IIC_LdStLHAU , [InstrStage<5, [SLU]>]>,
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InstrItinData<IIC_LdStLMW , [InstrStage<64, [SLU]>]>,
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InstrItinData<IIC_LdStLVecX , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStLWA , [InstrStage<5, [SLU]>]>,
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InstrItinData<IIC_LdStLWARX , [InstrStage<11, [SLU]>]>,
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InstrItinData<IIC_LdStSLBIA , [InstrStage<40, [SLU]>]>, // needs work
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InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [SLU]>]>,
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InstrItinData<IIC_LdStSTD , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStSTDU , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [SLU]>]>,
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InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [SLU]>]>,
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InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [SLU]>]>,
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InstrItinData<IIC_LdStSync , [InstrStage<35, [SLU]>]>,
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InstrItinData<IIC_SprISYNC , [InstrStage<40, [SLU]>]>, // needs work
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InstrItinData<IIC_SprMFSR , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_SprMTMSR , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_SprMTSR , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [SLU]>]>,
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InstrItinData<IIC_SprMFCR , [InstrStage<2, [IU2]>]>,
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InstrItinData<IIC_SprMFMSR , [InstrStage<3, [IU2]>]>,
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InstrItinData<IIC_SprMFSPR , [InstrStage<3, [IU2]>]>,
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InstrItinData<IIC_SprMFTB , [InstrStage<10, [IU2]>]>,
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InstrItinData<IIC_SprMTSPR , [InstrStage<8, [IU2]>]>,
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InstrItinData<IIC_SprSC , [InstrStage<1, [IU2]>]>,
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InstrItinData<IIC_FPGeneral , [InstrStage<6, [FPU1, FPU2]>]>,
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InstrItinData<IIC_FPAddSub , [InstrStage<6, [FPU1, FPU2]>]>,
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InstrItinData<IIC_FPCompare , [InstrStage<8, [FPU1, FPU2]>]>,
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InstrItinData<IIC_FPDivD , [InstrStage<33, [FPU1, FPU2]>]>,
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InstrItinData<IIC_FPDivS , [InstrStage<33, [FPU1, FPU2]>]>,
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InstrItinData<IIC_FPFused , [InstrStage<6, [FPU1, FPU2]>]>,
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InstrItinData<IIC_FPRes , [InstrStage<6, [FPU1, FPU2]>]>,
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InstrItinData<IIC_FPSqrt , [InstrStage<40, [FPU1, FPU2]>]>,
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InstrItinData<IIC_VecGeneral , [InstrStage<2, [VIU1]>]>,
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InstrItinData<IIC_VecFP , [InstrStage<8, [VFPU]>]>,
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InstrItinData<IIC_VecFPCompare, [InstrStage<2, [VFPU]>]>,
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InstrItinData<IIC_VecComplex , [InstrStage<5, [VIU2]>]>,
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InstrItinData<IIC_VecPerm , [InstrStage<3, [VPU]>]>,
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InstrItinData<IIC_VecFPRound , [InstrStage<8, [VFPU]>]>,
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InstrItinData<IIC_VecVSL , [InstrStage<2, [VIU1]>]>,
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InstrItinData<IIC_VecVSR , [InstrStage<3, [VPU]>]>
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]>;
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// ===---------------------------------------------------------------------===//
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// e5500 machine model for scheduling and other instruction cost heuristics.
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def G5Model : SchedMachineModel {
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let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle.
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let MinLatency = 0; // Out-of-order dispatch.
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let LoadLatency = 3; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let MispredictPenalty = 16;
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let Itineraries = G5Itineraries;
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}
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