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Remember the minimum cost of the registers in an allocation order and the number of registers at the end of the allocation order that have the same cost per use. This information can be used to limit the search space for RAGreedy::tryEvict() when looking for a cheaper register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172280 91177308-0d34-0410-b5e6-96231b3b80d8
147 lines
4.9 KiB
C++
147 lines
4.9 KiB
C++
//===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RegisterClassInfo class which provides dynamic
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// information about target register classes. Callee saved and reserved
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// registers depends on calling conventions and other dynamic information, so
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// some things cannot be determined statically.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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static cl::opt<unsigned>
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StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
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cl::desc("Limit all regclasses to N registers"));
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RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
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{}
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void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
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bool Update = false;
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MF = &mf;
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// Allocate new array the first time we see a new target.
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if (MF->getTarget().getRegisterInfo() != TRI) {
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TRI = MF->getTarget().getRegisterInfo();
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RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
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Update = true;
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}
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// Does this MF have different CSRs?
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const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
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if (Update || CSR != CalleeSaved) {
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// Build a CSRNum map. Every CSR alias gets an entry pointing to the last
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// overlapping CSR.
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CSRNum.clear();
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CSRNum.resize(TRI->getNumRegs(), 0);
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for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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CSRNum[*AI] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
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Update = true;
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}
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CalleeSaved = CSR;
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// Different reserved registers?
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const BitVector &RR = MF->getRegInfo().getReservedRegs();
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if (Reserved.size() != RR.size() || RR != Reserved) {
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Update = true;
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Reserved = RR;
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}
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// Invalidate cached information from previous function.
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if (Update)
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++Tag;
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}
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/// compute - Compute the preferred allocation order for RC with reserved
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/// registers filtered out. Volatile registers come first followed by CSR
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/// aliases ordered according to the CSR order specified by the target.
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void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
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RCInfo &RCI = RegClass[RC->getID()];
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// Raw register count, including all reserved regs.
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unsigned NumRegs = RC->getNumRegs();
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if (!RCI.Order)
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RCI.Order.reset(new MCPhysReg[NumRegs]);
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unsigned N = 0;
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SmallVector<MCPhysReg, 16> CSRAlias;
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unsigned MinCost = 0xff;
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unsigned LastCost = ~0u;
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unsigned LastCostChange = 0;
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// FIXME: Once targets reserve registers instead of removing them from the
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// allocation order, we can simply use begin/end here.
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ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
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for (unsigned i = 0; i != RawOrder.size(); ++i) {
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unsigned PhysReg = RawOrder[i];
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// Remove reserved registers from the allocation order.
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if (Reserved.test(PhysReg))
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continue;
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unsigned Cost = TRI->getCostPerUse(PhysReg);
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MinCost = std::min(MinCost, Cost);
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if (CSRNum[PhysReg])
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// PhysReg aliases a CSR, save it for later.
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CSRAlias.push_back(PhysReg);
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else {
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if (Cost != LastCost)
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LastCostChange = N;
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RCI.Order[N++] = PhysReg;
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LastCost = Cost;
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}
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}
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RCI.NumRegs = N + CSRAlias.size();
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assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
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// CSR aliases go after the volatile registers, preserve the target's order.
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for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
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unsigned PhysReg = CSRAlias[i];
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unsigned Cost = TRI->getCostPerUse(PhysReg);
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if (Cost != LastCost)
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LastCostChange = N;
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RCI.Order[N++] = PhysReg;
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LastCost = Cost;
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}
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// Register allocator stress test. Clip register class to N registers.
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if (StressRA && RCI.NumRegs > StressRA)
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RCI.NumRegs = StressRA;
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// Check if RC is a proper sub-class.
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if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
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if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
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RCI.ProperSubClass = true;
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RCI.MinCost = uint8_t(MinCost);
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RCI.LastCostChange = LastCostChange;
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DEBUG({
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dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
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for (unsigned I = 0; I != RCI.NumRegs; ++I)
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dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
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dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
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});
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// RCI is now up-to-date.
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RCI.Tag = Tag;
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}
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