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https://github.com/c64scene-ar/llvm-6502.git
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de95c1b88b
This is derived from a patch by Anton Korzh. I modified it to recognize the VEXT shuffles during legalization and lower them to a target-specific DAG node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79428 91177308-0d34-0410-b5e6-96231b3b80d8
310 lines
13 KiB
C++
310 lines
13 KiB
C++
//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that ARM uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMISELLOWERING_H
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#define ARMISELLOWERING_H
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#include "ARMSubtarget.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include <vector>
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namespace llvm {
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class ARMConstantPoolValue;
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namespace ARMISD {
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// ARM Specific DAG Nodes
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enum NodeType {
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// Start the numbering where the builtin ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
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// TargetExternalSymbol, and TargetGlobalAddress.
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WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
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CALL, // Function call.
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CALL_PRED, // Function call that's predicable.
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CALL_NOLINK, // Function call with branch not branch-and-link.
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tCALL, // Thumb function call.
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BRCOND, // Conditional branch.
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BR_JT, // Jumptable branch.
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BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
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RET_FLAG, // Return with a flag operand.
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PIC_ADD, // Add with a PC operand and a PIC label.
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CMP, // ARM compare instructions.
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CMPZ, // ARM compare that sets only Z flag.
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CMPFP, // ARM VFP compare instruction, sets FPSCR.
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CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
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FMSTAT, // ARM fmstat instruction.
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CMOV, // ARM conditional move instructions.
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CNEG, // ARM conditional negate instructions.
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FTOSI, // FP to sint within a FP register.
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FTOUI, // FP to uint within a FP register.
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SITOF, // sint to FP within a FP register.
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UITOF, // uint to FP within a FP register.
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SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
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SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
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RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
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FMRRD, // double to two gprs.
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FMDRR, // Two gprs to double.
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EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
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EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
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THREAD_POINTER,
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DYN_ALLOC, // Dynamic allocation on the stack.
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VCEQ, // Vector compare equal.
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VCGE, // Vector compare greater than or equal.
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VCGEU, // Vector compare unsigned greater than or equal.
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VCGT, // Vector compare greater than.
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VCGTU, // Vector compare unsigned greater than.
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VTST, // Vector test bits.
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// Vector shift by immediate:
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VSHL, // ...left
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VSHRs, // ...right (signed)
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VSHRu, // ...right (unsigned)
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VSHLLs, // ...left long (signed)
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VSHLLu, // ...left long (unsigned)
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VSHLLi, // ...left long (with maximum shift count)
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VSHRN, // ...right narrow
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// Vector rounding shift by immediate:
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VRSHRs, // ...right (signed)
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VRSHRu, // ...right (unsigned)
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VRSHRN, // ...right narrow
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// Vector saturating shift by immediate:
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VQSHLs, // ...left (signed)
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VQSHLu, // ...left (unsigned)
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VQSHLsu, // ...left (signed to unsigned)
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VQSHRNs, // ...right narrow (signed)
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VQSHRNu, // ...right narrow (unsigned)
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VQSHRNsu, // ...right narrow (signed to unsigned)
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// Vector saturating rounding shift by immediate:
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VQRSHRNs, // ...right narrow (signed)
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VQRSHRNu, // ...right narrow (unsigned)
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VQRSHRNsu, // ...right narrow (signed to unsigned)
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// Vector shift and insert:
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VSLI, // ...left
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VSRI, // ...right
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// Vector get lane (VMOV scalar to ARM core register)
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// (These are used for 8- and 16-bit element types only.)
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VGETLANEu, // zero-extend vector extract element
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VGETLANEs, // sign-extend vector extract element
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// Vector duplicate:
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VDUP,
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VDUPLANE,
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// Vector load/store with (de)interleaving
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VLD2D,
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VLD3D,
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VLD4D,
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VST2D,
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VST3D,
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VST4D,
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// Vector shuffles:
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VEXT, // extract
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VREV64, // reverse elements within 64-bit doublewords
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VREV32, // reverse elements within 32-bit words
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VREV16 // reverse elements within 16-bit halfwords
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};
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}
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/// Define some predicates that are used for node matching.
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namespace ARM {
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/// getVMOVImm - If this is a build_vector of constants which can be
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/// formed by using a VMOV instruction of the specified element size,
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/// return the constant being splatted. The ByteSize field indicates the
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/// number of bytes of each element [1248].
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SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
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}
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//===--------------------------------------------------------------------===//
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// ARMTargetLowering - ARM Implementation of the TargetLowering interface
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class ARMTargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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public:
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explicit ARMTargetLowering(TargetMachine &TM);
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
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/// ReplaceNodeResults - Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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///
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virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG);
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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/// allowsUnalignedMemoryAccesses - Returns true if the target allows
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/// unaligned memory accesses. of the specified type.
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/// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
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virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
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bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
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/// getPreIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if the node's address
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/// can be legally represented as pre-indexed load / store address.
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virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
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SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const;
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/// getPostIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if this node can be
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/// combined with a load / store to form a post-indexed load / store.
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virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
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SDValue &Base, SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const;
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virtual void computeMaskedBitsForTargetNode(const SDValue Op,
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const APInt &Mask,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const;
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
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/// true it means one of the asm constraint of the inline asm instruction
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/// being processed is 'm'.
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virtual void LowerAsmOperandForConstraint(SDValue Op,
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char ConstraintLetter,
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bool hasMemory,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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virtual const ARMSubtarget* getSubtarget() {
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return Subtarget;
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}
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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virtual unsigned getFunctionAlignment(const Function *F) const;
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private:
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const ARMSubtarget *Subtarget;
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/// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
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///
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unsigned ARMPCLabelIndex;
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void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
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void addDRTypeForNEON(EVT VT);
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void addQRTypeForNEON(EVT VT);
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typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
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void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
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SDValue Chain, SDValue &Arg,
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RegsToPassVector &RegsToPass,
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CCValAssign &VA, CCValAssign &NextVA,
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SDValue &StackPtr,
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SmallVector<SDValue, 8> &MemOpChains,
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ISD::ArgFlagsTy Flags);
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SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
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SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
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CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return, bool isVarArg) const;
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SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
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DebugLoc dl, SelectionDAG &DAG,
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const CCValAssign &VA,
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ISD::ArgFlagsTy Flags);
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SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
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SelectionDAG &DAG);
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SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
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SelectionDAG &DAG);
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SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
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SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
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SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
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SDValue Chain,
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SDValue Dst, SDValue Src,
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SDValue Size, unsigned Align,
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bool AlwaysInline,
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const Value *DstSV, uint64_t DstSVOff,
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const Value *SrcSV, uint64_t SrcSVOff);
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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unsigned CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals);
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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unsigned CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals);
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virtual SDValue
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LowerCall(SDValue Chain, SDValue Callee,
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unsigned CallConv, bool isVarArg,
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bool isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals);
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virtual SDValue
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LowerReturn(SDValue Chain,
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unsigned CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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DebugLoc dl, SelectionDAG &DAG);
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};
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}
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#endif // ARMISELLOWERING_H
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