llvm-6502/lib/CodeGen
Matt Arsenault 2dd264c8a3 Add alignment value to allowsUnalignedMemoryAccess
Rename to allowsMisalignedMemoryAccess.

On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment,
and don't need to be split into multiple accesses. Vector loads with
an alignment of the element type are not uncommon in OpenCL code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214055 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-27 17:46:40 +00:00
..
AsmPrinter Reapply "DebugInfo: Don't put fission type units in comdat sections." 2014-07-25 17:11:58 +00:00
SelectionDAG Add alignment value to allowsUnalignedMemoryAccess 2014-07-27 17:46:40 +00:00
AggressiveAntiDepBreaker.cpp
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp Remove TLI from isInTailCallPosition's arguments. NFC. 2014-07-16 00:01:22 +00:00
AntiDepBreaker.h
AtomicExpandLoadLinkedPass.cpp CodeGen: it turns out that NAND is not the same thing as BIC. At all. 2014-07-07 09:06:35 +00:00
BasicTargetTransformInfo.cpp Add @llvm.assume, lowering, and some basic properties 2014-07-25 21:13:35 +00:00
BranchFolding.cpp Prevent hoisting the instruction whose def might be clobbered by the terminator. 2014-06-05 13:42:48 +00:00
BranchFolding.h
CalcSpillWeights.cpp
CallingConvLower.cpp
CMakeLists.txt Templatify RegionInfo so it works on MachineBasicBlocks 2014-07-19 18:29:29 +00:00
CodeGen.cpp
CodeGenPrepare.cpp Revert "[C++11] Add predecessors(BasicBlock *) / successors(BasicBlock *) iterator ranges." 2014-07-21 17:06:51 +00:00
CriticalAntiDepBreaker.cpp bug fix for PR20020: anti-dependency-breaker causes miscompilation 2014-07-03 15:19:40 +00:00
CriticalAntiDepBreaker.h fixed a few typos in comments 2014-06-24 21:11:51 +00:00
DeadMachineInstructionElim.cpp
DFAPacketizer.cpp
DwarfEHPrepare.cpp
EarlyIfConversion.cpp Return false if we're not going to do anything. 2014-05-22 17:49:33 +00:00
EdgeBundles.cpp Convert several loops over MachineFunction basic blocks to range-based loops 2014-04-30 18:29:51 +00:00
ErlangGC.cpp
ExecutionDepsFix.cpp Clean up language and grammar. 2014-05-20 17:11:11 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp
GlobalMerge.cpp Fix some Twine locals. 2014-07-08 14:55:06 +00:00
IfConversion.cpp
InlineSpiller.cpp
InterferenceCache.cpp
InterferenceCache.h
IntrinsicLowering.cpp Add @llvm.assume, lowering, and some basic properties 2014-07-25 21:13:35 +00:00
JITCodeEmitter.cpp
JumpInstrTables.cpp [C++11] Use 'nullptr'. 2014-06-08 22:29:17 +00:00
LatencyPriorityQueue.cpp
LexicalScopes.cpp Revert "Reapply "DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself."""" 2014-07-18 23:57:20 +00:00
LiveDebugVariables.cpp Recommit r212203: Don't try to construct debug LexicalScopes hierarchy for functions that do not have top level debug information. 2014-07-25 16:10:16 +00:00
LiveDebugVariables.h Recommit r212203: Don't try to construct debug LexicalScopes hierarchy for functions that do not have top level debug information. 2014-07-25 16:10:16 +00:00
LiveInterval.cpp
LiveIntervalAnalysis.cpp Calculate dead instructions when a live interval is created. 2014-06-03 22:42:10 +00:00
LiveIntervalUnion.cpp
LivePhysRegs.cpp
LiveRangeCalc.cpp
LiveRangeCalc.h
LiveRangeEdit.cpp
LiveRegMatrix.cpp
LiveStackAnalysis.cpp
LiveVariables.cpp Convert more loops to range-based equivalents 2014-04-30 22:17:38 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp Allow a target to create a null streamer. 2014-06-20 13:11:28 +00:00
LocalStackSlotAllocation.cpp
MachineBasicBlock.cpp Fix missing const 2014-07-02 06:45:26 +00:00
MachineBlockFrequencyInfo.cpp Revert "Introduce a string_ostream string builder facilty" 2014-06-26 22:52:05 +00:00
MachineBlockPlacement.cpp Revert "Introduce a string_ostream string builder facilty" 2014-06-26 22:52:05 +00:00
MachineBranchProbabilityInfo.cpp
MachineCodeEmitter.cpp
MachineCopyPropagation.cpp
MachineCSE.cpp
MachineDominanceFrontier.cpp Templatify DominanceFrontier. 2014-07-12 21:59:52 +00:00
MachineDominators.cpp
MachineFunction.cpp AA metadata refactoring (introduce AAMDNodes) 2014-07-24 12:16:19 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Add scoped-noalias metadata 2014-07-24 14:25:39 +00:00
MachineInstrBundle.cpp
MachineLICM.cpp
MachineLoopInfo.cpp
MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegionInfo.cpp MachineRegionInfo.cpp: Another fix on MachineRegionInfo::MachineRegionInfo::recalculate() to appease msc17. 2014-07-20 11:14:55 +00:00
MachineRegisterInfo.cpp
MachineScheduler.cpp Revert "Revert "MachineScheduler: better book-keeping for asserts."" 2014-07-02 16:46:08 +00:00
MachineSink.cpp
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp Convert more loops to range-based equivalents 2014-04-30 22:17:38 +00:00
MachineVerifier.cpp MachineVerifier: Clean up some syntactic weirdness left behind by find&replace. 2014-05-24 13:31:10 +00:00
Makefile
module.modulemap [modules] Add module maps for LLVM. These are not quite ready for prime-time 2014-05-21 02:46:14 +00:00
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp Add scoped-noalias metadata 2014-07-24 14:25:39 +00:00
PeepholeOptimizer.cpp [PeepholeOptimzer] Fix a typo in a comment. 2014-07-01 16:23:44 +00:00
PHIElimination.cpp Convert more loops to range-based equivalents 2014-04-30 22:17:38 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp Move Post RA Scheduling flag bit into SchedMachineModel 2014-07-15 22:39:58 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp Re-apply r211399, "Generate native unwind info on Win64" with a fix to ignore SEH pseudo ops in X86 JIT emitter. 2014-06-25 12:41:52 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp
RegAllocBase.h
RegAllocBasic.cpp Remove uses of the redundant ".reset(nullptr)" of unique_ptr, in favor of ".reset()" 2014-07-19 01:05:11 +00:00
RegAllocFast.cpp
RegAllocGreedy.cpp Remove uses of the redundant ".reset(nullptr)" of unique_ptr, in favor of ".reset()" 2014-07-19 01:05:11 +00:00
RegAllocPBQP.cpp Sure up ownership passing of the PBQPBuilder by passing unique_ptrs by value rather than lvalue reference. 2014-07-19 21:19:45 +00:00
RegisterClassInfo.cpp
RegisterCoalescer.cpp [RegisterCoalescer] Moving the RegisterCoalescer subtarget hook onto the TargetRegisterInfo instead of the TargetSubtargetInfo. 2014-07-16 20:13:31 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Move remaining LLVM_ENABLE_DUMP conditionals out of the headers 2014-07-01 21:19:13 +00:00
RegisterScavenging.cpp
ScheduleDAG.cpp
ScheduleDAGInstrs.cpp AA metadata refactoring (introduce AAMDNodes) 2014-07-24 12:16:19 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp
SjLjEHPrepare.cpp Revert "[C++11] Add predecessors(BasicBlock *) / successors(BasicBlock *) iterator ranges." 2014-07-21 17:06:51 +00:00
SlotIndexes.cpp
Spiller.cpp
Spiller.h
SpillPlacement.cpp
SpillPlacement.h
SplitKit.cpp
SplitKit.h Clean up language and grammar. 2014-05-20 17:11:11 +00:00
StackColoring.cpp
StackMapLivenessAnalysis.cpp [StackMaps] Enable patchpoint liveness analysis per default. 2014-06-26 23:39:52 +00:00
StackMaps.cpp [Stackmaps] Pacify windows buildbot. 2014-05-01 22:39:26 +00:00
StackProtector.cpp
StackSlotColoring.cpp
TailDuplication.cpp Convert more loops to range-based equivalents 2014-04-30 22:17:38 +00:00
TargetFrameLoweringImpl.cpp
TargetInstrInfo.cpp Remove the query for TargetMachine and TargetInstrInfo since we're 2014-07-23 22:12:03 +00:00
TargetLoweringBase.cpp CodeGen: emit IR-level f16 conversion intrinsics as fptrunc/fpext 2014-07-21 09:13:56 +00:00
TargetLoweringObjectFileImpl.cpp CodeGen: Stick constant pool entries in COMDAT sections for WinCOFF 2014-07-14 22:57:27 +00:00
TargetOptionsImpl.cpp
TargetRegisterInfo.cpp
TargetSchedule.cpp Revert "Introduce a string_ostream string builder facilty" 2014-06-26 22:52:05 +00:00
TwoAddressInstructionPass.cpp
UnreachableBlockElim.cpp Revert "[C++11] Add predecessors(BasicBlock *) / successors(BasicBlock *) iterator ranges." 2014-07-21 17:06:51 +00:00
VirtRegMap.cpp

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.