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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
76 lines
1.8 KiB
LLVM
76 lines
1.8 KiB
LLVM
; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
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; CHECK-LABEL: f:
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define float @f(<4 x i16>* nocapture %in) {
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; CHECK: vldr
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; CHECK: vmovl.u16
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%1 = load <4 x i16>, <4 x i16>* %in
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; CHECK: vcvt.f32.u32
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%2 = uitofp <4 x i16> %1 to <4 x float>
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%3 = extractelement <4 x float> %2, i32 0
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%4 = extractelement <4 x float> %2, i32 1
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%5 = extractelement <4 x float> %2, i32 2
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; CHECK: vadd.f32
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%6 = fadd float %3, %4
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%7 = fadd float %6, %5
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ret float %7
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}
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; CHECK-LABEL: g:
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define float @g(<4 x i8>* nocapture %in) {
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; Note: vld1 here is reasonably important. Mixing VFP and NEON
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; instructions is bad on some cores
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; CHECK: vld1
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; CHECK: vmovl.u8
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; CHECK: vmovl.u16
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%1 = load <4 x i8>, <4 x i8>* %in
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; CHECK: vcvt.f32.u32
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%2 = uitofp <4 x i8> %1 to <4 x float>
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%3 = extractelement <4 x float> %2, i32 0
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%4 = extractelement <4 x float> %2, i32 1
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%5 = extractelement <4 x float> %2, i32 2
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; CHECK: vadd.f32
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%6 = fadd float %3, %4
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%7 = fadd float %6, %5
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ret float %7
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}
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; CHECK-LABEL: h:
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define <4 x i8> @h(<4 x float> %v) {
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; CHECK: vcvt.{{[us]}}32.f32
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; CHECK: vmovn.i32
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%1 = fptoui <4 x float> %v to <4 x i8>
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ret <4 x i8> %1
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}
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; CHECK-LABEL: i:
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define <4 x i8> @i(<4 x i8>* %x) {
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; Note: vld1 here is reasonably important. Mixing VFP and NEON
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; instructions is bad on some cores
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; CHECK: vld1
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; CHECK: vmovl.s8
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; CHECK: vmovl.s16
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; CHECK: vrecpe
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; CHECK: vrecps
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; CHECK: vmul
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; CHECK: vmovn
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%1 = load <4 x i8>, <4 x i8>* %x, align 4
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%2 = sdiv <4 x i8> zeroinitializer, %1
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ret <4 x i8> %2
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}
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; CHECK-LABEL: j:
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define <4 x i32> @j(<4 x i8>* %in) nounwind {
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; CHECK: vld1
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; CHECK: vmovl.u8
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; CHECK: vmovl.u16
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; CHECK-NOT: vand
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%1 = load <4 x i8>, <4 x i8>* %in, align 4
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%2 = zext <4 x i8> %1 to <4 x i32>
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ret <4 x i32> %2
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}
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