mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8e58179048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5148 91177308-0d34-0410-b5e6-96231b3b80d8
121 lines
4.1 KiB
C++
121 lines
4.1 KiB
C++
//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
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//
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// This file contains the X86 implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86RegisterInfo.h"
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#include "X86InstrBuilder.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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static unsigned getIdx(const TargetRegisterClass *RC) {
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switch (RC->getDataSize()) {
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default: assert(0 && "Invalid data size!");
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case 1: return 0;
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case 2: return 1;
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case 4: return 2;
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case 10: return 3;
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}
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}
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void X86RegisterInfo::storeReg2RegOffset(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned SrcReg, unsigned DestReg,
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unsigned ImmOffset,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] =
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{ X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTPr80 };
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MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(RC)], 5),
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DestReg, ImmOffset).addReg(SrcReg);
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MBBI = MBB.insert(MBBI, MI)+1;
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}
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void X86RegisterInfo::loadRegOffset2Reg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, unsigned SrcReg,
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unsigned ImmOffset,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] =
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{ X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr80 };
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MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(RC)], 4, DestReg),
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SrcReg, ImmOffset);
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MBBI = MBB.insert(MBBI, MI)+1;
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}
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void X86RegisterInfo::moveReg2Reg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] =
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{ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
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MachineInstr *MI = BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg);
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MBBI = MBB.insert(MBBI, MI)+1;
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}
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void X86RegisterInfo::moveImm2Reg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, unsigned Imm,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] =
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{ X86::MOVir8, X86::MOVir16, X86::MOVir32, 0 };
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MachineInstr *MI = BuildMI(Opcode[getIdx(RC)], 1, DestReg).addReg(Imm);
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assert(MI->getOpcode() != 0 && "Cannot move FP imm to reg yet!");
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MBBI = MBB.insert(MBBI, MI)+1;
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}
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unsigned X86RegisterInfo::getFramePointer() const {
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return X86::EBP;
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}
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unsigned X86RegisterInfo::getStackPointer() const {
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return X86::ESP;
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}
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const unsigned* X86RegisterInfo::getCalleeSaveRegs() const {
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static const unsigned CalleeSaveRegs[] = { X86::ESI, X86::EDI, X86::EBX, 0 };
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return CalleeSaveRegs;
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}
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const unsigned* X86RegisterInfo::getCallerSaveRegs() const {
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static const unsigned CallerSaveRegs[] = { X86::EAX, X86::ECX, X86::EDX, 0 };
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return CallerSaveRegs;
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}
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void X86RegisterInfo::emitPrologue(MachineFunction &MF,
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unsigned NumBytes) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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// Round stack allocation up to a nice alignment to keep the stack aligned
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NumBytes = (NumBytes + 3) & ~3;
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// PUSH ebp
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MachineInstr *MI = BuildMI(X86::PUSHr32, 1).addReg(X86::EBP);
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MBBI = MBB.insert(MBBI, MI)+1;
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// MOV ebp, esp
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MI = BuildMI(X86::MOVrr32, 1, X86::EBP).addReg(X86::ESP);
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MBBI = MBB.insert(MBBI, MI)+1;
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// adjust stack pointer: ESP -= numbytes
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MI = BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes);
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MBBI = 1+MBB.insert(MBBI, MI);
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}
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void X86RegisterInfo::emitEpilogue(MachineBasicBlock &MBB,
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unsigned numBytes) const {
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MachineBasicBlock::iterator MBBI = MBB.end()-1;
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assert((*MBBI)->getOpcode() == X86::RET &&
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"Can only insert epilog into returning blocks");
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// insert LEAVE: mov ESP, EBP; pop EBP
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MBBI = 1+MBB.insert(MBBI, BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP));
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MBBI = 1+MBB.insert(MBBI, BuildMI(X86::POPr32, 1).addReg(X86::EBP));
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}
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