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sets as keys into a cache of interference matrice values in the Interference constraint adder. Creating interference matrices was one of the large remaining time-sinks in PBQP. Caching them reduces the total compile time (when using PBQP) on the nightly test suite by ~10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220688 91177308-0d34-0410-b5e6-96231b3b80d8
704 lines
24 KiB
C++
704 lines
24 KiB
C++
//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
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// register allocator for LLVM. This allocator works by constructing a PBQP
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// problem representing the register allocation problem under consideration,
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// solving this using a PBQP solver, and mapping the solution back to a
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// register assignment. If any variables are selected for spilling then spill
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// code is inserted and the process repeated.
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//
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// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
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// for register allocation. For more information on PBQP for register
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// allocation, see the following papers:
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//
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// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
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// PBQP. In Proceedings of the 7th Joint Modular Languages Conference
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// (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
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//
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// (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
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// architectures. In Proceedings of the Joint Conference on Languages,
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// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
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// NY, USA, 139-148.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/RegAllocPBQP.h"
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#include "RegisterCoalescer.h"
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#include "Spiller.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveRangeEdit.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/FileSystem.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <limits>
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#include <memory>
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#include <queue>
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#include <set>
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#include <sstream>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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static RegisterRegAlloc
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RegisterPBQPRepAlloc("pbqp", "PBQP register allocator",
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createDefaultPBQPRegisterAllocator);
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static cl::opt<bool>
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PBQPCoalescing("pbqp-coalescing",
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cl::desc("Attempt coalescing during PBQP register allocation."),
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cl::init(false), cl::Hidden);
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#ifndef NDEBUG
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static cl::opt<bool>
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PBQPDumpGraphs("pbqp-dump-graphs",
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cl::desc("Dump graphs for each function/round in the compilation unit."),
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cl::init(false), cl::Hidden);
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#endif
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namespace {
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///
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/// PBQP based allocators solve the register allocation problem by mapping
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/// register allocation problems to Partitioned Boolean Quadratic
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/// Programming problems.
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class RegAllocPBQP : public MachineFunctionPass {
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public:
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static char ID;
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/// Construct a PBQP register allocator.
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RegAllocPBQP(char *cPassID = nullptr)
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: MachineFunctionPass(ID), customPassID(cPassID) {
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initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
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initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
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initializeLiveStacksPass(*PassRegistry::getPassRegistry());
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initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
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}
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/// Return the pass name.
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const char* getPassName() const override {
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return "PBQP Register Allocator";
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}
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/// PBQP analysis usage.
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void getAnalysisUsage(AnalysisUsage &au) const override;
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/// Perform register allocation
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
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typedef std::vector<const LiveInterval*> Node2LIMap;
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typedef std::vector<unsigned> AllowedSet;
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typedef std::vector<AllowedSet> AllowedSetMap;
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typedef std::pair<unsigned, unsigned> RegPair;
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typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
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typedef std::set<unsigned> RegSet;
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char *customPassID;
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RegSet VRegsToAlloc, EmptyIntervalVRegs;
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/// \brief Finds the initial set of vreg intervals to allocate.
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void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
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/// \brief Constructs an initial graph.
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void initializeGraph(PBQPRAGraph &G);
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/// \brief Given a solved PBQP problem maps this solution back to a register
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/// assignment.
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bool mapPBQPToRegAlloc(const PBQPRAGraph &G,
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const PBQP::Solution &Solution,
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VirtRegMap &VRM,
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Spiller &VRegSpiller);
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/// \brief Postprocessing before final spilling. Sets basic block "live in"
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/// variables.
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void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
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VirtRegMap &VRM) const;
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};
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char RegAllocPBQP::ID = 0;
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/// @brief Set spill costs for each node in the PBQP reg-alloc graph.
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class SpillCosts : public PBQPRAConstraint {
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public:
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void apply(PBQPRAGraph &G) override {
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LiveIntervals &LIS = G.getMetadata().LIS;
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for (auto NId : G.nodeIds()) {
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PBQP::PBQPNum SpillCost =
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LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight;
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if (SpillCost == 0.0)
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SpillCost = std::numeric_limits<PBQP::PBQPNum>::min();
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PBQPRAGraph::RawVector NodeCosts(G.getNodeCosts(NId));
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NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost;
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G.setNodeCosts(NId, std::move(NodeCosts));
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}
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}
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};
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/// @brief Add interference edges between overlapping vregs.
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class Interference : public PBQPRAConstraint {
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private:
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private:
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typedef const PBQP::RegAlloc::AllowedRegVector* AllowedRegVecPtr;
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typedef std::pair<AllowedRegVecPtr, AllowedRegVecPtr> IMatrixKey;
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typedef DenseMap<IMatrixKey, PBQPRAGraph::MatrixPtr> IMatrixCache;
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// Holds (Interval, CurrentSegmentID, and NodeId). The first two are required
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// for the fast interference graph construction algorithm. The last is there
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// to save us from looking up node ids via the VRegToNode map in the graph
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// metadata.
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typedef std::tuple<LiveInterval*, size_t, PBQP::GraphBase::NodeId>
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IntervalInfo;
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static SlotIndex getStartPoint(const IntervalInfo &I) {
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return std::get<0>(I)->segments[std::get<1>(I)].start;
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}
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static SlotIndex getEndPoint(const IntervalInfo &I) {
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return std::get<0>(I)->segments[std::get<1>(I)].end;
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}
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static PBQP::GraphBase::NodeId getNodeId(const IntervalInfo &I) {
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return std::get<2>(I);
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}
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static bool lowestStartPoint(const IntervalInfo &I1,
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const IntervalInfo &I2) {
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// Condition reversed because priority queue has the *highest* element at
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// the front, rather than the lowest.
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return getStartPoint(I1) > getStartPoint(I2);
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}
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static bool lowestEndPoint(const IntervalInfo &I1,
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const IntervalInfo &I2) {
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SlotIndex E1 = getEndPoint(I1);
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SlotIndex E2 = getEndPoint(I2);
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if (E1 < E2)
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return true;
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if (E1 > E2)
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return false;
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// If two intervals end at the same point, we need a way to break the tie or
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// the set will assume they're actually equal and refuse to insert a
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// "duplicate". Just compare the vregs - fast and guaranteed unique.
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return std::get<0>(I1)->reg < std::get<0>(I2)->reg;
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}
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static bool isAtLastSegment(const IntervalInfo &I) {
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return std::get<1>(I) == std::get<0>(I)->size() - 1;
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}
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static IntervalInfo nextSegment(const IntervalInfo &I) {
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return std::make_tuple(std::get<0>(I), std::get<1>(I) + 1, std::get<2>(I));
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}
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public:
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void apply(PBQPRAGraph &G) override {
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// The following is loosely based on the linear scan algorithm introduced in
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// "Linear Scan Register Allocation" by Poletto and Sarkar. This version
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// isn't linear, because the size of the active set isn't bound by the
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// number of registers, but rather the size of the largest clique in the
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// graph. Still, we expect this to be better than N^2.
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LiveIntervals &LIS = G.getMetadata().LIS;
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// Interferenc matrices are incredibly regular - they're only a function of
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// the allowed sets, so we cache them to avoid the overhead of constructing
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// and uniquing them.
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IMatrixCache C;
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typedef std::set<IntervalInfo, decltype(&lowestEndPoint)> IntervalSet;
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typedef std::priority_queue<IntervalInfo, std::vector<IntervalInfo>,
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decltype(&lowestStartPoint)> IntervalQueue;
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IntervalSet Active(lowestEndPoint);
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IntervalQueue Inactive(lowestStartPoint);
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// Start by building the inactive set.
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for (auto NId : G.nodeIds()) {
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unsigned VReg = G.getNodeMetadata(NId).getVReg();
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LiveInterval &LI = LIS.getInterval(VReg);
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assert(!LI.empty() && "PBQP graph contains node for empty interval");
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Inactive.push(std::make_tuple(&LI, 0, NId));
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}
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while (!Inactive.empty()) {
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// Tentatively grab the "next" interval - this choice may be overriden
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// below.
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IntervalInfo Cur = Inactive.top();
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// Retire any active intervals that end before Cur starts.
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IntervalSet::iterator RetireItr = Active.begin();
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while (RetireItr != Active.end() &&
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(getEndPoint(*RetireItr) <= getStartPoint(Cur))) {
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// If this interval has subsequent segments, add the next one to the
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// inactive list.
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if (!isAtLastSegment(*RetireItr))
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Inactive.push(nextSegment(*RetireItr));
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++RetireItr;
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}
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Active.erase(Active.begin(), RetireItr);
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// One of the newly retired segments may actually start before the
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// Cur segment, so re-grab the front of the inactive list.
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Cur = Inactive.top();
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Inactive.pop();
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// At this point we know that Cur overlaps all active intervals. Add the
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// interference edges.
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PBQP::GraphBase::NodeId NId = getNodeId(Cur);
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for (const auto &A : Active) {
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PBQP::GraphBase::NodeId MId = getNodeId(A);
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// Check that we haven't already added this edge
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// FIXME: findEdge is expensive in the worst case (O(max_clique(G))).
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// It might be better to replace this with a local bit-matrix.
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if (G.findEdge(NId, MId) != PBQPRAGraph::invalidEdgeId())
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continue;
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// This is a new edge - add it to the graph.
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createInterferenceEdge(G, NId, MId, C);
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}
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// Finally, add Cur to the Active set.
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Active.insert(Cur);
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}
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}
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private:
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void createInterferenceEdge(PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
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PBQPRAGraph::NodeId MId, IMatrixCache &C) {
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const TargetRegisterInfo &TRI =
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*G.getMetadata().MF.getTarget().getSubtargetImpl()->getRegisterInfo();
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const auto &NRegs = G.getNodeMetadata(NId).getAllowedRegs();
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const auto &MRegs = G.getNodeMetadata(MId).getAllowedRegs();
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// Try looking the edge costs up in the IMatrixCache first.
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IMatrixKey K(&NRegs, &MRegs);
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IMatrixCache::iterator I = C.find(K);
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if (I != C.end()) {
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G.addEdgeBypassingCostAllocator(NId, MId, I->second);
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return;
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}
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PBQPRAGraph::RawMatrix M(NRegs.size() + 1, MRegs.size() + 1, 0);
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for (unsigned I = 0; I != NRegs.size(); ++I) {
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unsigned PRegN = NRegs[I];
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for (unsigned J = 0; J != MRegs.size(); ++J) {
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unsigned PRegM = MRegs[J];
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if (TRI.regsOverlap(PRegN, PRegM))
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M[I + 1][J + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
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}
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}
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PBQPRAGraph::EdgeId EId = G.addEdge(NId, MId, std::move(M));
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C[K] = G.getEdgeCostsPtr(EId);
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}
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};
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class Coalescing : public PBQPRAConstraint {
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public:
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void apply(PBQPRAGraph &G) override {
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MachineFunction &MF = G.getMetadata().MF;
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MachineBlockFrequencyInfo &MBFI = G.getMetadata().MBFI;
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CoalescerPair CP(*MF.getTarget().getSubtargetImpl()->getRegisterInfo());
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// Scan the machine function and add a coalescing cost whenever CoalescerPair
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// gives the Ok.
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for (const auto &MBB : MF) {
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for (const auto &MI : MBB) {
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// Skip not-coalescable or already coalesced copies.
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if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg())
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continue;
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unsigned DstReg = CP.getDstReg();
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unsigned SrcReg = CP.getSrcReg();
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const float CopyFactor = 0.5; // Cost of copy relative to load. Current
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// value plucked randomly out of the air.
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PBQP::PBQPNum CBenefit =
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CopyFactor * LiveIntervals::getSpillWeight(false, true, &MBFI, &MI);
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if (CP.isPhys()) {
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if (!MF.getRegInfo().isAllocatable(DstReg))
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continue;
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PBQPRAGraph::NodeId NId = G.getMetadata().getNodeIdForVReg(SrcReg);
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const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed =
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G.getNodeMetadata(NId).getAllowedRegs();
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unsigned PRegOpt = 0;
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while (PRegOpt < Allowed.size() && Allowed[PRegOpt] != DstReg)
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++PRegOpt;
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if (PRegOpt < Allowed.size()) {
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PBQPRAGraph::RawVector NewCosts(G.getNodeCosts(NId));
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NewCosts[PRegOpt + 1] -= CBenefit;
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G.setNodeCosts(NId, std::move(NewCosts));
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}
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} else {
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PBQPRAGraph::NodeId N1Id = G.getMetadata().getNodeIdForVReg(DstReg);
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PBQPRAGraph::NodeId N2Id = G.getMetadata().getNodeIdForVReg(SrcReg);
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const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed1 =
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&G.getNodeMetadata(N1Id).getAllowedRegs();
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const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed2 =
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&G.getNodeMetadata(N2Id).getAllowedRegs();
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PBQPRAGraph::EdgeId EId = G.findEdge(N1Id, N2Id);
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if (EId == G.invalidEdgeId()) {
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PBQPRAGraph::RawMatrix Costs(Allowed1->size() + 1,
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Allowed2->size() + 1, 0);
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addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
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G.addEdge(N1Id, N2Id, std::move(Costs));
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} else {
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if (G.getEdgeNode1Id(EId) == N2Id) {
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std::swap(N1Id, N2Id);
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std::swap(Allowed1, Allowed2);
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}
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PBQPRAGraph::RawMatrix Costs(G.getEdgeCosts(EId));
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addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
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G.setEdgeCosts(EId, std::move(Costs));
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}
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}
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}
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}
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}
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private:
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void addVirtRegCoalesce(
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PBQPRAGraph::RawMatrix &CostMat,
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const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed1,
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const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed2,
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PBQP::PBQPNum Benefit) {
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assert(CostMat.getRows() == Allowed1.size() + 1 && "Size mismatch.");
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assert(CostMat.getCols() == Allowed2.size() + 1 && "Size mismatch.");
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for (unsigned I = 0; I != Allowed1.size(); ++I) {
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unsigned PReg1 = Allowed1[I];
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for (unsigned J = 0; J != Allowed2.size(); ++J) {
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unsigned PReg2 = Allowed2[J];
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if (PReg1 == PReg2)
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CostMat[I + 1][J + 1] -= Benefit;
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}
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}
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}
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};
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} // End anonymous namespace.
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// Out-of-line destructor/anchor for PBQPRAConstraint.
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PBQPRAConstraint::~PBQPRAConstraint() {}
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void PBQPRAConstraint::anchor() {}
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void PBQPRAConstraintList::anchor() {}
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void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
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au.setPreservesCFG();
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au.addRequired<AliasAnalysis>();
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au.addPreserved<AliasAnalysis>();
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au.addRequired<SlotIndexes>();
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au.addPreserved<SlotIndexes>();
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au.addRequired<LiveIntervals>();
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au.addPreserved<LiveIntervals>();
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//au.addRequiredID(SplitCriticalEdgesID);
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if (customPassID)
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au.addRequiredID(*customPassID);
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au.addRequired<LiveStacks>();
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au.addPreserved<LiveStacks>();
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au.addRequired<MachineBlockFrequencyInfo>();
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au.addPreserved<MachineBlockFrequencyInfo>();
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au.addRequired<MachineLoopInfo>();
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au.addPreserved<MachineLoopInfo>();
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au.addRequired<MachineDominatorTree>();
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au.addPreserved<MachineDominatorTree>();
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au.addRequired<VirtRegMap>();
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au.addPreserved<VirtRegMap>();
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MachineFunctionPass::getAnalysisUsage(au);
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}
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void RegAllocPBQP::findVRegIntervalsToAlloc(const MachineFunction &MF,
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LiveIntervals &LIS) {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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// Iterate over all live ranges.
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
|
|
if (MRI.reg_nodbg_empty(Reg))
|
|
continue;
|
|
LiveInterval &LI = LIS.getInterval(Reg);
|
|
|
|
// If this live interval is non-empty we will use pbqp to allocate it.
|
|
// Empty intervals we allocate in a simple post-processing stage in
|
|
// finalizeAlloc.
|
|
if (!LI.empty()) {
|
|
VRegsToAlloc.insert(LI.reg);
|
|
} else {
|
|
EmptyIntervalVRegs.insert(LI.reg);
|
|
}
|
|
}
|
|
}
|
|
|
|
void RegAllocPBQP::initializeGraph(PBQPRAGraph &G) {
|
|
MachineFunction &MF = G.getMetadata().MF;
|
|
|
|
LiveIntervals &LIS = G.getMetadata().LIS;
|
|
const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
|
|
const TargetRegisterInfo &TRI =
|
|
*G.getMetadata().MF.getTarget().getSubtargetImpl()->getRegisterInfo();
|
|
|
|
for (auto VReg : VRegsToAlloc) {
|
|
const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
|
|
LiveInterval &VRegLI = LIS.getInterval(VReg);
|
|
|
|
// Record any overlaps with regmask operands.
|
|
BitVector RegMaskOverlaps;
|
|
LIS.checkRegMaskInterference(VRegLI, RegMaskOverlaps);
|
|
|
|
// Compute an initial allowed set for the current vreg.
|
|
std::vector<unsigned> VRegAllowed;
|
|
ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
|
|
for (unsigned I = 0; I != RawPRegOrder.size(); ++I) {
|
|
unsigned PReg = RawPRegOrder[I];
|
|
if (MRI.isReserved(PReg))
|
|
continue;
|
|
|
|
// vregLI crosses a regmask operand that clobbers preg.
|
|
if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg))
|
|
continue;
|
|
|
|
// vregLI overlaps fixed regunit interference.
|
|
bool Interference = false;
|
|
for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
|
|
if (VRegLI.overlaps(LIS.getRegUnit(*Units))) {
|
|
Interference = true;
|
|
break;
|
|
}
|
|
}
|
|
if (Interference)
|
|
continue;
|
|
|
|
// preg is usable for this virtual register.
|
|
VRegAllowed.push_back(PReg);
|
|
}
|
|
|
|
PBQPRAGraph::RawVector NodeCosts(VRegAllowed.size() + 1, 0);
|
|
PBQPRAGraph::NodeId NId = G.addNode(std::move(NodeCosts));
|
|
G.getNodeMetadata(NId).setVReg(VReg);
|
|
G.getNodeMetadata(NId).setAllowedRegs(
|
|
G.getMetadata().getAllowedRegs(std::move(VRegAllowed)));
|
|
G.getMetadata().setNodeIdForVReg(VReg, NId);
|
|
}
|
|
}
|
|
|
|
bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G,
|
|
const PBQP::Solution &Solution,
|
|
VirtRegMap &VRM,
|
|
Spiller &VRegSpiller) {
|
|
MachineFunction &MF = G.getMetadata().MF;
|
|
LiveIntervals &LIS = G.getMetadata().LIS;
|
|
const TargetRegisterInfo &TRI =
|
|
*MF.getTarget().getSubtargetImpl()->getRegisterInfo();
|
|
(void)TRI;
|
|
|
|
// Set to true if we have any spills
|
|
bool AnotherRoundNeeded = false;
|
|
|
|
// Clear the existing allocation.
|
|
VRM.clearAllVirt();
|
|
|
|
// Iterate over the nodes mapping the PBQP solution to a register
|
|
// assignment.
|
|
for (auto NId : G.nodeIds()) {
|
|
unsigned VReg = G.getNodeMetadata(NId).getVReg();
|
|
unsigned AllocOption = Solution.getSelection(NId);
|
|
|
|
if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) {
|
|
unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1];
|
|
DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> "
|
|
<< TRI.getName(PReg) << "\n");
|
|
assert(PReg != 0 && "Invalid preg selected.");
|
|
VRM.assignVirt2Phys(VReg, PReg);
|
|
} else {
|
|
VRegsToAlloc.erase(VReg);
|
|
SmallVector<unsigned, 8> NewSpills;
|
|
LiveRangeEdit LRE(&LIS.getInterval(VReg), NewSpills, MF, LIS, &VRM);
|
|
VRegSpiller.spill(LRE);
|
|
|
|
DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: "
|
|
<< LRE.getParent().weight << ", New vregs: ");
|
|
|
|
// Copy any newly inserted live intervals into the list of regs to
|
|
// allocate.
|
|
for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end();
|
|
I != E; ++I) {
|
|
LiveInterval &LI = LIS.getInterval(*I);
|
|
assert(!LI.empty() && "Empty spill range.");
|
|
DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " ");
|
|
VRegsToAlloc.insert(LI.reg);
|
|
}
|
|
|
|
DEBUG(dbgs() << ")\n");
|
|
|
|
// We need another round if spill intervals were added.
|
|
AnotherRoundNeeded |= !LRE.empty();
|
|
}
|
|
}
|
|
|
|
return !AnotherRoundNeeded;
|
|
}
|
|
|
|
void RegAllocPBQP::finalizeAlloc(MachineFunction &MF,
|
|
LiveIntervals &LIS,
|
|
VirtRegMap &VRM) const {
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
// First allocate registers for the empty intervals.
|
|
for (RegSet::const_iterator
|
|
I = EmptyIntervalVRegs.begin(), E = EmptyIntervalVRegs.end();
|
|
I != E; ++I) {
|
|
LiveInterval &LI = LIS.getInterval(*I);
|
|
|
|
unsigned PReg = MRI.getSimpleHint(LI.reg);
|
|
|
|
if (PReg == 0) {
|
|
const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
|
|
PReg = RC.getRawAllocationOrder(MF).front();
|
|
}
|
|
|
|
VRM.assignVirt2Phys(LI.reg, PReg);
|
|
}
|
|
}
|
|
|
|
bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
|
|
LiveIntervals &LIS = getAnalysis<LiveIntervals>();
|
|
MachineBlockFrequencyInfo &MBFI =
|
|
getAnalysis<MachineBlockFrequencyInfo>();
|
|
|
|
calculateSpillWeightsAndHints(LIS, MF, getAnalysis<MachineLoopInfo>(), MBFI);
|
|
|
|
VirtRegMap &VRM = getAnalysis<VirtRegMap>();
|
|
|
|
std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));
|
|
|
|
MF.getRegInfo().freezeReservedRegs(MF);
|
|
|
|
DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n");
|
|
|
|
// Allocator main loop:
|
|
//
|
|
// * Map current regalloc problem to a PBQP problem
|
|
// * Solve the PBQP problem
|
|
// * Map the solution back to a register allocation
|
|
// * Spill if necessary
|
|
//
|
|
// This process is continued till no more spills are generated.
|
|
|
|
// Find the vreg intervals in need of allocation.
|
|
findVRegIntervalsToAlloc(MF, LIS);
|
|
|
|
#ifndef NDEBUG
|
|
const Function &F = *MF.getFunction();
|
|
std::string FullyQualifiedName =
|
|
F.getParent()->getModuleIdentifier() + "." + F.getName().str();
|
|
#endif
|
|
|
|
// If there are non-empty intervals allocate them using pbqp.
|
|
if (!VRegsToAlloc.empty()) {
|
|
|
|
const TargetSubtargetInfo &Subtarget = *MF.getTarget().getSubtargetImpl();
|
|
std::unique_ptr<PBQPRAConstraintList> ConstraintsRoot =
|
|
llvm::make_unique<PBQPRAConstraintList>();
|
|
ConstraintsRoot->addConstraint(llvm::make_unique<SpillCosts>());
|
|
ConstraintsRoot->addConstraint(llvm::make_unique<Interference>());
|
|
if (PBQPCoalescing)
|
|
ConstraintsRoot->addConstraint(llvm::make_unique<Coalescing>());
|
|
ConstraintsRoot->addConstraint(Subtarget.getCustomPBQPConstraints());
|
|
|
|
bool PBQPAllocComplete = false;
|
|
unsigned Round = 0;
|
|
|
|
while (!PBQPAllocComplete) {
|
|
DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n");
|
|
|
|
PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI));
|
|
initializeGraph(G);
|
|
ConstraintsRoot->apply(G);
|
|
|
|
#ifndef NDEBUG
|
|
if (PBQPDumpGraphs) {
|
|
std::ostringstream RS;
|
|
RS << Round;
|
|
std::string GraphFileName = FullyQualifiedName + "." + RS.str() +
|
|
".pbqpgraph";
|
|
std::error_code EC;
|
|
raw_fd_ostream OS(GraphFileName, EC, sys::fs::F_Text);
|
|
DEBUG(dbgs() << "Dumping graph for round " << Round << " to \""
|
|
<< GraphFileName << "\"\n");
|
|
G.dumpToStream(OS);
|
|
}
|
|
#endif
|
|
|
|
PBQP::Solution Solution = PBQP::RegAlloc::solve(G);
|
|
PBQPAllocComplete = mapPBQPToRegAlloc(G, Solution, VRM, *VRegSpiller);
|
|
++Round;
|
|
}
|
|
}
|
|
|
|
// Finalise allocation, allocate empty ranges.
|
|
finalizeAlloc(MF, LIS, VRM);
|
|
VRegsToAlloc.clear();
|
|
EmptyIntervalVRegs.clear();
|
|
|
|
DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n");
|
|
|
|
return true;
|
|
}
|
|
|
|
FunctionPass *llvm::createPBQPRegisterAllocator(char *customPassID) {
|
|
return new RegAllocPBQP(customPassID);
|
|
}
|
|
|
|
FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
|
|
return createPBQPRegisterAllocator();
|
|
}
|
|
|
|
#undef DEBUG_TYPE
|