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Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
298 lines
11 KiB
C++
298 lines
11 KiB
C++
//===-- MBlazeInstrInfo.cpp - MBlaze Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MBlaze implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MBlazeInstrInfo.h"
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#include "MBlazeMachineFunction.h"
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#include "MBlazeTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_INSTRINFO_CTOR
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#include "MBlazeGenInstrInfo.inc"
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using namespace llvm;
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MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm)
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: MBlazeGenInstrInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
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TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImm() && op.getImm() == 0;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned MBlazeInstrInfo::
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const {
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if (MI->getOpcode() == MBlaze::LWI) {
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2)))) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned MBlazeInstrInfo::
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const {
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if (MI->getOpcode() == MBlaze::SWI) {
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2)))) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// insertNoop - If data hazard condition is found insert the target nop
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/// instruction.
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void MBlazeInstrInfo::
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insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
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DebugLoc DL;
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BuildMI(MBB, MI, DL, get(MBlaze::NOP));
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}
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void MBlazeInstrInfo::
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copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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llvm::BuildMI(MBB, I, DL, get(MBlaze::ADDK), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc)).addReg(MBlaze::R0);
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}
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void MBlazeInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0); //.addFrameIndex(FI);
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}
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void MBlazeInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
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.addFrameIndex(FI).addImm(0); //.addFrameIndex(FI);
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}
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//===----------------------------------------------------------------------===//
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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bool MBlazeInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin())
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return false;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return false;
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--I;
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}
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if (!isUnpredicatedTerminator(I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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unsigned LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (MBlaze::isUncondBranchOpcode(LastOpc)) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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if (MBlaze::isCondBranchOpcode(LastOpc)) {
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
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Cond.push_back(LastInst->getOperand(0));
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return false;
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}
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// Otherwise, don't know what this is.
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return true;
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}
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// Get the instruction before it if it's a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
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return true;
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// If the block ends with something like BEQID then BRID, handle it.
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if (MBlaze::isCondBranchOpcode(SecondLastInst->getOpcode()) &&
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MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
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TBB = SecondLastInst->getOperand(1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
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Cond.push_back(SecondLastInst->getOperand(0));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two unconditional branches, handle it.
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// The second one is not executed, so remove it.
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if (MBlaze::isUncondBranchOpcode(SecondLastInst->getOpcode()) &&
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MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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unsigned MBlazeInstrInfo::
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InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"MBlaze branch conditions have two components!");
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unsigned Opc = MBlaze::BRID;
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if (!Cond.empty())
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Opc = (unsigned)Cond[0].getImm();
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if (FBB == 0) {
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if (Cond.empty()) // Unconditional branch
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BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
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else // Conditional branch
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BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
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return 1;
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}
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BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
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BuildMI(&MBB, DL, get(MBlaze::BRID)).addMBB(FBB);
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return 2;
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}
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unsigned MBlazeInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return 0;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return 0;
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--I;
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}
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if (!MBlaze::isUncondBranchOpcode(I->getOpcode()) &&
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!MBlaze::isCondBranchOpcode(I->getOpcode()))
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return 1;
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--I;
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if (!MBlaze::isCondBranchOpcode(I->getOpcode()))
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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bool MBlazeInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand>
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&Cond) const {
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assert(Cond.size() == 2 && "Invalid MBlaze branch opcode!");
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switch (Cond[0].getImm()) {
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default: return true;
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case MBlaze::BEQ: Cond[0].setImm(MBlaze::BNE); return false;
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case MBlaze::BNE: Cond[0].setImm(MBlaze::BEQ); return false;
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case MBlaze::BGT: Cond[0].setImm(MBlaze::BLE); return false;
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case MBlaze::BGE: Cond[0].setImm(MBlaze::BLT); return false;
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case MBlaze::BLT: Cond[0].setImm(MBlaze::BGE); return false;
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case MBlaze::BLE: Cond[0].setImm(MBlaze::BGT); return false;
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case MBlaze::BEQI: Cond[0].setImm(MBlaze::BNEI); return false;
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case MBlaze::BNEI: Cond[0].setImm(MBlaze::BEQI); return false;
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case MBlaze::BGTI: Cond[0].setImm(MBlaze::BLEI); return false;
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case MBlaze::BGEI: Cond[0].setImm(MBlaze::BLTI); return false;
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case MBlaze::BLTI: Cond[0].setImm(MBlaze::BGEI); return false;
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case MBlaze::BLEI: Cond[0].setImm(MBlaze::BGTI); return false;
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case MBlaze::BEQD: Cond[0].setImm(MBlaze::BNED); return false;
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case MBlaze::BNED: Cond[0].setImm(MBlaze::BEQD); return false;
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case MBlaze::BGTD: Cond[0].setImm(MBlaze::BLED); return false;
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case MBlaze::BGED: Cond[0].setImm(MBlaze::BLTD); return false;
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case MBlaze::BLTD: Cond[0].setImm(MBlaze::BGED); return false;
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case MBlaze::BLED: Cond[0].setImm(MBlaze::BGTD); return false;
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case MBlaze::BEQID: Cond[0].setImm(MBlaze::BNEID); return false;
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case MBlaze::BNEID: Cond[0].setImm(MBlaze::BEQID); return false;
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case MBlaze::BGTID: Cond[0].setImm(MBlaze::BLEID); return false;
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case MBlaze::BGEID: Cond[0].setImm(MBlaze::BLTID); return false;
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case MBlaze::BLTID: Cond[0].setImm(MBlaze::BGEID); return false;
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case MBlaze::BLEID: Cond[0].setImm(MBlaze::BGTID); return false;
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}
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}
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/// getGlobalBaseReg - Return a virtual register initialized with the
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/// the global base register value. Output instructions required to
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/// initialize the register in the function entry block, if necessary.
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///
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unsigned MBlazeInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
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MBlazeFunctionInfo *MBlazeFI = MF->getInfo<MBlazeFunctionInfo>();
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unsigned GlobalBaseReg = MBlazeFI->getGlobalBaseReg();
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if (GlobalBaseReg != 0)
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return GlobalBaseReg;
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = MF->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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GlobalBaseReg = RegInfo.createVirtualRegister(&MBlaze::GPRRegClass);
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BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
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GlobalBaseReg).addReg(MBlaze::R20);
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RegInfo.addLiveIn(MBlaze::R20);
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MBlazeFI->setGlobalBaseReg(GlobalBaseReg);
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return GlobalBaseReg;
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}
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