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The goal of the patch is to implement section 3.2.3 of the AMD64 ABI correctly. The controlling sentence is, "The size of each argument gets rounded up to eightbytes. Therefore the stack will always be eightbyte aligned." The equivalent sentence in the i386 ABI page 37 says, "At all times, the stack pointer should point to a word-aligned area." For both architectures, the stack pointer is not being rounded up to the nearest eightbyte or word between the last normal argument and the first variadic argument. Patch by Thomas Jablin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216119 91177308-0d34-0410-b5e6-96231b3b80d8
474 lines
16 KiB
C++
474 lines
16 KiB
C++
//===-- llvm/CallingConvLower.h - Calling Conventions -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the CCState and CCValAssign classes, used for lowering
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// and implementing calling conventions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
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#define LLVM_CODEGEN_CALLINGCONVLOWER_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/Target/TargetCallingConv.h"
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namespace llvm {
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class CCState;
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class MVT;
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class TargetMachine;
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class TargetRegisterInfo;
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/// CCValAssign - Represent assignment of one arg/retval to a location.
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class CCValAssign {
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public:
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enum LocInfo {
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Full, // The value fills the full location.
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SExt, // The value is sign extended in the location.
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ZExt, // The value is zero extended in the location.
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AExt, // The value is extended with undefined upper bits.
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BCvt, // The value is bit-converted in the location.
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VExt, // The value is vector-widened in the location.
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// FIXME: Not implemented yet. Code that uses AExt to mean
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// vector-widen should be fixed to use VExt instead.
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FPExt, // The floating-point value is fp-extended in the location.
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Indirect // The location contains pointer to the value.
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// TODO: a subset of the value is in the location.
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};
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private:
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/// ValNo - This is the value number begin assigned (e.g. an argument number).
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unsigned ValNo;
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/// Loc is either a stack offset or a register number.
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unsigned Loc;
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/// isMem - True if this is a memory loc, false if it is a register loc.
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unsigned isMem : 1;
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/// isCustom - True if this arg/retval requires special handling.
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unsigned isCustom : 1;
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/// Information about how the value is assigned.
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LocInfo HTP : 6;
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/// ValVT - The type of the value being assigned.
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MVT ValVT;
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/// LocVT - The type of the location being assigned to.
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MVT LocVT;
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public:
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static CCValAssign getReg(unsigned ValNo, MVT ValVT,
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unsigned RegNo, MVT LocVT,
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LocInfo HTP) {
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CCValAssign Ret;
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Ret.ValNo = ValNo;
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Ret.Loc = RegNo;
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Ret.isMem = false;
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Ret.isCustom = false;
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Ret.HTP = HTP;
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Ret.ValVT = ValVT;
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Ret.LocVT = LocVT;
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return Ret;
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}
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static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
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unsigned RegNo, MVT LocVT,
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LocInfo HTP) {
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CCValAssign Ret;
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Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
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Ret.isCustom = true;
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return Ret;
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}
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static CCValAssign getMem(unsigned ValNo, MVT ValVT,
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unsigned Offset, MVT LocVT,
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LocInfo HTP) {
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CCValAssign Ret;
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Ret.ValNo = ValNo;
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Ret.Loc = Offset;
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Ret.isMem = true;
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Ret.isCustom = false;
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Ret.HTP = HTP;
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Ret.ValVT = ValVT;
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Ret.LocVT = LocVT;
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return Ret;
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}
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static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
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unsigned Offset, MVT LocVT,
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LocInfo HTP) {
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CCValAssign Ret;
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Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
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Ret.isCustom = true;
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return Ret;
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}
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// There is no need to differentiate between a pending CCValAssign and other
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// kinds, as they are stored in a different list.
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static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT,
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LocInfo HTP) {
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return getReg(ValNo, ValVT, 0, LocVT, HTP);
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}
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void convertToReg(unsigned RegNo) {
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Loc = RegNo;
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isMem = false;
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}
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void convertToMem(unsigned Offset) {
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Loc = Offset;
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isMem = true;
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}
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unsigned getValNo() const { return ValNo; }
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MVT getValVT() const { return ValVT; }
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bool isRegLoc() const { return !isMem; }
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bool isMemLoc() const { return isMem; }
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bool needsCustom() const { return isCustom; }
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unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
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unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
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MVT getLocVT() const { return LocVT; }
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LocInfo getLocInfo() const { return HTP; }
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bool isExtInLoc() const {
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return (HTP == AExt || HTP == SExt || HTP == ZExt);
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}
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};
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/// CCAssignFn - This function assigns a location for Val, updating State to
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/// reflect the change. It returns 'true' if it failed to handle Val.
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typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
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MVT LocVT, CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags, CCState &State);
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/// CCCustomFn - This function assigns a location for Val, possibly updating
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/// all args to reflect changes and indicates if it handled it. It must set
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/// isCustom if it handles the arg and returns true.
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typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
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MVT &LocVT, CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State);
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/// ParmContext - This enum tracks whether calling convention lowering is in
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/// the context of prologue or call generation. Not all backends make use of
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/// this information.
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typedef enum { Unknown, Prologue, Call } ParmContext;
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/// CCState - This class holds information needed while lowering arguments and
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/// return values. It captures which registers are already assigned and which
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/// stack slots are used. It provides accessors to allocate these values.
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class CCState {
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private:
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CallingConv::ID CallingConv;
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bool IsVarArg;
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MachineFunction &MF;
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const TargetRegisterInfo &TRI;
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SmallVectorImpl<CCValAssign> &Locs;
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LLVMContext &Context;
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unsigned StackOffset;
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SmallVector<uint32_t, 16> UsedRegs;
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SmallVector<CCValAssign, 4> PendingLocs;
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// ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
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//
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// Vector of ByValInfo instances (ByValRegs) is introduced for byval registers
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// tracking.
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// Or, in another words it tracks byval parameters that are stored in
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// general purpose registers.
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//
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// For 4 byte stack alignment,
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// instance index means byval parameter number in formal
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// arguments set. Assume, we have some "struct_type" with size = 4 bytes,
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// then, for function "foo":
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//
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// i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t)
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//
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// ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2)
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// ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
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//
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// In case of 8 bytes stack alignment,
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// ByValRegs may also contain information about wasted registers.
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// In function shown above, r3 would be wasted according to AAPCS rules.
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// And in that case ByValRegs[1].Waste would be "true".
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// ByValRegs vector size still would be 2,
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// while "%t" goes to the stack: it wouldn't be described in ByValRegs.
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//
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// Supposed use-case for this collection:
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// 1. Initially ByValRegs is empty, InRegsParamsProceed is 0.
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// 2. HandleByVal fillups ByValRegs.
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// 3. Argument analysis (LowerFormatArguments, for example). After
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// some byval argument was analyzed, InRegsParamsProceed is increased.
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struct ByValInfo {
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ByValInfo(unsigned B, unsigned E, bool IsWaste = false) :
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Begin(B), End(E), Waste(IsWaste) {}
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// First register allocated for current parameter.
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unsigned Begin;
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// First after last register allocated for current parameter.
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unsigned End;
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// Means that current range of registers doesn't belong to any
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// parameters. It was wasted due to stack alignment rules.
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// For more information see:
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// AAPCS, 5.5 Parameter Passing, Stage C, C.3.
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bool Waste;
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};
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SmallVector<ByValInfo, 4 > ByValRegs;
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// InRegsParamsProceed - shows how many instances of ByValRegs was proceed
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// during argument analysis.
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unsigned InRegsParamsProceed;
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protected:
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ParmContext CallOrPrologue;
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public:
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CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
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SmallVectorImpl<CCValAssign> &locs, LLVMContext &C);
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void addLoc(const CCValAssign &V) {
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Locs.push_back(V);
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}
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LLVMContext &getContext() const { return Context; }
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MachineFunction &getMachineFunction() const { return MF; }
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CallingConv::ID getCallingConv() const { return CallingConv; }
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bool isVarArg() const { return IsVarArg; }
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unsigned getNextStackOffset() const { return StackOffset; }
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/// isAllocated - Return true if the specified register (or an alias) is
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/// allocated.
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bool isAllocated(unsigned Reg) const {
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return UsedRegs[Reg/32] & (1 << (Reg&31));
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}
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/// AnalyzeFormalArguments - Analyze an array of argument values,
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/// incorporating info about the formals into this state.
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void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
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CCAssignFn Fn);
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/// AnalyzeReturn - Analyze the returned values of a return,
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/// incorporating info about the result values into this state.
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void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn);
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/// CheckReturn - Analyze the return values of a function, returning
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/// true if the return can be performed without sret-demotion, and
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/// false otherwise.
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bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
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CCAssignFn Fn);
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/// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
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/// incorporating info about the passed values into this state.
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void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn);
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/// AnalyzeCallOperands - Same as above except it takes vectors of types
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/// and argument flags.
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void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
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SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
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CCAssignFn Fn);
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/// AnalyzeCallResult - Analyze the return values of a call,
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/// incorporating info about the passed values into this state.
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void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
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CCAssignFn Fn);
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/// AnalyzeCallResult - Same as above except it's specialized for calls which
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/// produce a single value.
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void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
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/// getFirstUnallocated - Return the first unallocated register in the set, or
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/// NumRegs if they are all allocated.
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unsigned getFirstUnallocated(const MCPhysReg *Regs, unsigned NumRegs) const {
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for (unsigned i = 0; i != NumRegs; ++i)
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if (!isAllocated(Regs[i]))
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return i;
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return NumRegs;
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}
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/// AllocateReg - Attempt to allocate one register. If it is not available,
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/// return zero. Otherwise, return the register, marking it and any aliases
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/// as allocated.
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unsigned AllocateReg(unsigned Reg) {
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if (isAllocated(Reg)) return 0;
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MarkAllocated(Reg);
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return Reg;
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}
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/// Version of AllocateReg with extra register to be shadowed.
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unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
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if (isAllocated(Reg)) return 0;
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MarkAllocated(Reg);
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MarkAllocated(ShadowReg);
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return Reg;
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}
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/// AllocateReg - Attempt to allocate one of the specified registers. If none
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/// are available, return zero. Otherwise, return the first one available,
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/// marking it and any aliases as allocated.
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unsigned AllocateReg(const MCPhysReg *Regs, unsigned NumRegs) {
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unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
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if (FirstUnalloc == NumRegs)
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return 0; // Didn't find the reg.
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// Mark the register and any aliases as allocated.
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unsigned Reg = Regs[FirstUnalloc];
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MarkAllocated(Reg);
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return Reg;
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}
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/// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
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/// registers. If this is not possible, return zero. Otherwise, return the first
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/// register of the block that were allocated, marking the entire block as allocated.
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unsigned AllocateRegBlock(const uint16_t *Regs, unsigned NumRegs, unsigned RegsRequired) {
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for (unsigned StartIdx = 0; StartIdx <= NumRegs - RegsRequired; ++StartIdx) {
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bool BlockAvailable = true;
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// Check for already-allocated regs in this block
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for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
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if (isAllocated(Regs[StartIdx + BlockIdx])) {
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BlockAvailable = false;
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break;
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}
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}
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if (BlockAvailable) {
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// Mark the entire block as allocated
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for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
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MarkAllocated(Regs[StartIdx + BlockIdx]);
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}
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return Regs[StartIdx];
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}
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}
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// No block was available
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return 0;
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}
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/// Version of AllocateReg with list of registers to be shadowed.
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unsigned AllocateReg(const MCPhysReg *Regs, const MCPhysReg *ShadowRegs,
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unsigned NumRegs) {
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unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
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if (FirstUnalloc == NumRegs)
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return 0; // Didn't find the reg.
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// Mark the register and any aliases as allocated.
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unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
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MarkAllocated(Reg);
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MarkAllocated(ShadowReg);
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return Reg;
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}
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/// AlignStack - Align the top of the stakc to the specified alignment.
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void AlignStack(unsigned Align) {
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assert(Align && ((Align - 1) & Align) == 0); // Align is power of 2.
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StackOffset = ((StackOffset + Align - 1) & ~(Align - 1));
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}
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/// AllocateStack - Allocate a chunk of stack space with the specified size
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/// and alignment.
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unsigned AllocateStack(unsigned Size, unsigned Align) {
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AlignStack(Align);
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unsigned Result = StackOffset;
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StackOffset += Size;
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MF.getFrameInfo()->ensureMaxAlignment(Align);
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return Result;
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}
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/// Version of AllocateStack with extra register to be shadowed.
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unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) {
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MarkAllocated(ShadowReg);
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return AllocateStack(Size, Align);
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}
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/// Version of AllocateStack with list of extra registers to be shadowed.
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/// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
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unsigned AllocateStack(unsigned Size, unsigned Align,
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const MCPhysReg *ShadowRegs, unsigned NumShadowRegs) {
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for (unsigned i = 0; i < NumShadowRegs; ++i)
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MarkAllocated(ShadowRegs[i]);
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return AllocateStack(Size, Align);
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}
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// HandleByVal - Allocate a stack slot large enough to pass an argument by
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// value. The size and alignment information of the argument is encoded in its
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// parameter attribute.
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void HandleByVal(unsigned ValNo, MVT ValVT,
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MVT LocVT, CCValAssign::LocInfo LocInfo,
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int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
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// Returns count of byval arguments that are to be stored (even partly)
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// in registers.
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unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
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// Returns count of byval in-regs arguments proceed.
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unsigned getInRegsParamsProceed() const { return InRegsParamsProceed; }
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// Get information about N-th byval parameter that is stored in registers.
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// Here "ByValParamIndex" is N.
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void getInRegsParamInfo(unsigned InRegsParamRecordIndex,
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unsigned& BeginReg, unsigned& EndReg) const {
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assert(InRegsParamRecordIndex < ByValRegs.size() &&
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"Wrong ByVal parameter index");
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const ByValInfo& info = ByValRegs[InRegsParamRecordIndex];
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BeginReg = info.Begin;
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EndReg = info.End;
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}
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// Add information about parameter that is kept in registers.
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void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) {
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ByValRegs.push_back(ByValInfo(RegBegin, RegEnd));
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}
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// Goes either to next byval parameter (excluding "waste" record), or
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// to the end of collection.
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// Returns false, if end is reached.
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bool nextInRegsParam() {
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unsigned e = ByValRegs.size();
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if (InRegsParamsProceed < e)
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++InRegsParamsProceed;
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return InRegsParamsProceed < e;
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}
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// Clear byval registers tracking info.
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void clearByValRegsInfo() {
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InRegsParamsProceed = 0;
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ByValRegs.clear();
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}
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// Rewind byval registers tracking info.
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void rewindByValRegsInfo() {
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InRegsParamsProceed = 0;
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}
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ParmContext getCallOrPrologue() const { return CallOrPrologue; }
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// Get list of pending assignments
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SmallVectorImpl<llvm::CCValAssign> &getPendingLocs() {
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return PendingLocs;
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}
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private:
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/// MarkAllocated - Mark a register and all of its aliases as allocated.
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void MarkAllocated(unsigned Reg);
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};
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} // end namespace llvm
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#endif
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