Matt Arsenault db1807144a R600/SI: Fix 64-bit bit ops that require the VALU. ... Try to match scalar and first like the other instructions. Expand 64-bit ands to a pair of 32-bit ands since that is not available on the VALU. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204660 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-24 20:08:05 +00:00
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AArch64	[AArch64] Add SchedRW lists to NEON instructions.	2014-03-21 19:34:41 +00:00
ARM
CPP
Generic
Hexagon
Inputs
Mips	[mips] Correct lowering of VECTOR_SHUFFLE to VSHF.	2014-03-21 16:56:51 +00:00
MSP430
NVPTX	Add test to test/CodeGen/NVPTX for "alloca buffer" arguments.	2014-03-24 16:52:30 +00:00
PowerPC	[PowerPC] Make use of VSX f64 <-> i64 conversion instructions	2014-03-23 05:35:00 +00:00
R600	R600/SI: Fix 64-bit bit ops that require the VALU.	2014-03-24 20:08:05 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	[X86][ISelDAG] Add missing fallback patterns for avx2 broadcast instructions.	2014-03-24 17:54:19 +00:00
XCore