mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f89da7210b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179361 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.9 KiB
LLVM
49 lines
1.9 KiB
LLVM
;; RUN: llc -mtriple=armv7-linux-gnueabi -O3 \
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;; RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 -arm-reserve-r9 \
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;; RUN: -filetype=obj %s -o - | \
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;; RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
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;; FIXME: This file needs to be in .s form!
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;; The args to llc are there to constrain the codegen only.
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;;
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;; Ensure no regression on ARM/gcc compatibility for
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;; emitting explicit symbol relocs for nonexternal symbols
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;; versus section symbol relocs (with offset) -
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;;
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;; Default llvm behavior is to emit as section symbol relocs nearly
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;; everything that is not an undefined external. Unfortunately, this
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;; diverges from what codesourcery ARM/gcc does!
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;;
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;; Tests that reloc to .L.str* show up as explicit symbols
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target triple = "armv7-none-linux-gnueabi"
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@.str = private constant [7 x i8] c"@null\0A\00", align 4
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@.str1 = private constant [8 x i8] c"@write\0A\00", align 4
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@.str2 = private constant [13 x i8] c"hello worldn\00", align 4
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@.str3 = private constant [7 x i8] c"@exit\0A\00", align 4
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declare i32 @mystrlen(i8* nocapture %s) nounwind readonly
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declare void @myhextochar(i32 %n, i8* nocapture %buffer) nounwind
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define i32 @main() nounwind {
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entry:
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%0 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 6) nounwind
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%1 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([8 x i8]* @.str1, i32 0, i32 0), i32 7) nounwind
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%2 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([13 x i8]* @.str2, i32 0, i32 0), i32 12) nounwind
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%3 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([7 x i8]* @.str3, i32 0, i32 0), i32 6) nounwind
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tail call void @exit(i32 55) noreturn nounwind
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unreachable
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}
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declare i32 @write(...)
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declare void @exit(i32) noreturn nounwind
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;; OBJ: Relocations [
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;; OBJ: Section (1) .text {
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;; OBJ-NEXT: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC .L.str
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;; OBJ: }
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;; OBJ: ]
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