Evan Cheng 86050dc8cc Allow ARM if-converter to be run after post allocation scheduling. ... - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8		2010-06-18 23:09:54 +00:00
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Mangler.h
SubtargetFeature.h	The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a	2010-05-11 00:30:02 +00:00
Target.td	Reapply r105521, this time appending "LLU" to 64 bit	2010-06-08 22:51:23 +00:00
TargetAsmBackend.h	MC: Change RelaxInstruction to only take the input and output instructions.	2010-05-26 18:15:06 +00:00
TargetAsmLexer.h
TargetAsmParser.h
TargetCallingConv.td
TargetData.h
TargetELFWriterInfo.h
TargetFrameInfo.h
TargetInstrDesc.h	Start TargetRegisterClass indices at 0 instead of 1, so that	2010-06-18 18:13:55 +00:00
TargetInstrInfo.h	Allow ARM if-converter to be run after post allocation scheduling.	2010-06-18 23:09:54 +00:00
TargetInstrItineraries.h	declare a class with 'class' instead of struct to avoid tag mismatch	2010-06-12 15:46:56 +00:00
TargetIntrinsicInfo.h
TargetJITInfo.h
TargetLowering.h	Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,	2010-06-18 01:05:21 +00:00
TargetLoweringObjectFile.h	Add a new section and accessor for TLS data.	2010-05-22 00:00:58 +00:00
TargetMachine.h	MC: Add TargetMachine support for setting the value of MCRelaxAll with	2010-05-26 21:48:55 +00:00
TargetOpcodes.h	- Fix description of SUBREG_TO_REG. It's not going to generate a zext. But it	2010-06-09 18:15:36 +00:00
TargetOptions.h
TargetRegisterInfo.h	Start TargetRegisterClass indices at 0 instead of 1, so that	2010-06-18 18:13:55 +00:00
TargetRegistry.h	Currently, createMachOStreamer() is invoked directly in llvm-mc which	2010-05-21 12:54:43 +00:00
TargetSchedule.td
TargetSelect.h
TargetSelectionDAG.td
TargetSelectionDAGInfo.h	Fix a comment.	2010-05-11 18:03:41 +00:00
TargetSubtarget.h