mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0552d51c45
to use the information in the module rather than TargetOptions. We've had and clang has used the use-soft-float attribute for some time now so have the backends set a subtarget feature based on a particular function now that subtargets are created based on functions and function attributes. For the one middle end soft float check go ahead and create an overloadable TargetLowering::useSoftFloat function that just checks the TargetSubtargetInfo in all cases. Also remove the command line option that hard codes whether or not soft-float is set by using the attribute for all of the target specific test cases - for the generic just go ahead and add the attribute in the one case that showed up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237079 91177308-0d34-0410-b5e6-96231b3b80d8
408 lines
15 KiB
C++
408 lines
15 KiB
C++
//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMFrameLowering.h"
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#include "ARMTargetMachine.h"
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#include "ARMTargetObjectFile.h"
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#include "ARMTargetTransformInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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static cl::opt<bool>
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DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
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cl::desc("Inhibit optimization of S->D register accesses on A15"),
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cl::init(false));
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static cl::opt<bool>
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EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
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cl::desc("Run SimplifyCFG after expanding atomic operations"
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" to make use of cmpxchg flow-based information"),
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cl::init(true));
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static cl::opt<bool>
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EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
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cl::desc("Enable ARM load/store optimization pass"),
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cl::init(true));
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// FIXME: Unify control over GlobalMerge.
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static cl::opt<cl::boolOrDefault>
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EnableGlobalMerge("arm-global-merge", cl::Hidden,
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cl::desc("Enable the global merge pass"));
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extern "C" void LLVMInitializeARMTarget() {
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// Register the target.
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RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
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RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
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RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
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RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
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}
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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if (TT.isOSBinFormatMachO())
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return make_unique<TargetLoweringObjectFileMachO>();
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if (TT.isOSWindows())
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return make_unique<TargetLoweringObjectFileCOFF>();
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return make_unique<ARMElfTargetObjectFile>();
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}
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static ARMBaseTargetMachine::ARMABI
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computeTargetABI(const Triple &TT, StringRef CPU,
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const TargetOptions &Options) {
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if (Options.MCOptions.getABIName().startswith("aapcs"))
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return ARMBaseTargetMachine::ARM_ABI_AAPCS;
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else if (Options.MCOptions.getABIName().startswith("apcs"))
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return ARMBaseTargetMachine::ARM_ABI_APCS;
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assert(Options.MCOptions.getABIName().empty() &&
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"Unknown target-abi option!");
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ARMBaseTargetMachine::ARMABI TargetABI =
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ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
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// FIXME: This is duplicated code from the front end and should be unified.
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if (TT.isOSBinFormatMachO()) {
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if (TT.getEnvironment() == llvm::Triple::EABI ||
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(TT.getOS() == llvm::Triple::UnknownOS &&
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TT.getObjectFormat() == llvm::Triple::MachO) ||
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CPU.startswith("cortex-m")) {
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TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
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} else {
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TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
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}
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} else if (TT.isOSWindows()) {
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// FIXME: this is invalid for WindowsCE
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TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
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} else {
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// Select the default based on the platform.
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switch (TT.getEnvironment()) {
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case llvm::Triple::Android:
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case llvm::Triple::GNUEABI:
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case llvm::Triple::GNUEABIHF:
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case llvm::Triple::EABIHF:
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case llvm::Triple::EABI:
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TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
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break;
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case llvm::Triple::GNU:
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TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
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break;
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default:
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if (TT.getOS() == llvm::Triple::NetBSD)
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TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
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else
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TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
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break;
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}
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}
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return TargetABI;
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}
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static std::string computeDataLayout(StringRef TT, StringRef CPU,
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const TargetOptions &Options,
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bool isLittle) {
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const Triple Triple(TT);
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auto ABI = computeTargetABI(Triple, CPU, Options);
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std::string Ret = "";
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if (isLittle)
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// Little endian.
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Ret += "e";
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else
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// Big endian.
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Ret += "E";
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Ret += DataLayout::getManglingComponent(Triple);
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// Pointers are 32 bits and aligned to 32 bits.
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Ret += "-p:32:32";
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// ABIs other than APCS have 64 bit integers with natural alignment.
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if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
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Ret += "-i64:64";
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// We have 64 bits floats. The APCS ABI requires them to be aligned to 32
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// bits, others to 64 bits. We always try to align to 64 bits.
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if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
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Ret += "-f64:32:64";
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// We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
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// to 64. We always ty to give them natural alignment.
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if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
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Ret += "-v64:32:64-v128:32:128";
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else
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Ret += "-v128:64:128";
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// Try to align aggregates to 32 bits (the default is 64 bits, which has no
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// particular hardware support on 32-bit ARM).
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Ret += "-a:0:32";
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// Integer registers are 32 bits.
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Ret += "-n32";
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// The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
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// aligned everywhere else.
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if (Triple.isOSNaCl())
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Ret += "-S128";
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else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
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Ret += "-S64";
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else
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Ret += "-S32";
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return Ret;
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}
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/// TargetMachine ctor - Create an ARM architecture model.
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///
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ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool isLittle)
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: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
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CPU, FS, Options, RM, CM, OL),
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TargetABI(computeTargetABI(Triple(TT), CPU, Options)),
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TLOF(createTLOF(Triple(getTargetTriple()))),
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Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
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// Default to triple-appropriate float ABI
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if (Options.FloatABIType == FloatABI::Default)
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this->Options.FloatABIType =
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Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
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}
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ARMBaseTargetMachine::~ARMBaseTargetMachine() {}
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const ARMSubtarget *
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ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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// FIXME: This is related to the code below to reset the target options,
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// we need to know whether or not the soft float flag is set on the
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// function before we can generate a subtarget. We also need to use
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// it as a key for the subtarget since that can be the only difference
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// between two functions.
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bool SoftFloat =
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F.hasFnAttribute("use-soft-float") &&
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F.getFnAttribute("use-soft-float").getValueAsString() == "true";
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// If the soft float attribute is set on the function turn on the soft float
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// subtarget feature.
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if (SoftFloat)
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FS += FS.empty() ? "+soft-float" : ",+soft-float";
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
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}
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return I.get();
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}
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TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
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return TargetIRAnalysis(
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[this](Function &F) { return TargetTransformInfo(ARMTTIImpl(this, F)); });
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}
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void ARMTargetMachine::anchor() { }
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ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool isLittle)
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: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
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initAsmInfo();
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if (!Subtarget.hasARMOps())
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report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
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"support ARM mode execution!");
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}
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void ARMLETargetMachine::anchor() { }
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ARMLETargetMachine::ARMLETargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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void ARMBETargetMachine::anchor() { }
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ARMBETargetMachine::ARMBETargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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void ThumbTargetMachine::anchor() { }
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ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool isLittle)
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: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL,
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isLittle) {
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initAsmInfo();
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}
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void ThumbLETargetMachine::anchor() { }
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ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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void ThumbBETargetMachine::anchor() { }
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ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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namespace {
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/// ARM Code Generator Pass Configuration Options.
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class ARMPassConfig : public TargetPassConfig {
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public:
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ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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ARMBaseTargetMachine &getARMTargetMachine() const {
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return getTM<ARMBaseTargetMachine>();
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}
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const ARMSubtarget &getARMSubtarget() const {
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return *getARMTargetMachine().getSubtargetImpl();
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}
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void addIRPasses() override;
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bool addPreISel() override;
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bool addInstSelector() override;
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void addPreRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new ARMPassConfig(this, PM);
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}
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void ARMPassConfig::addIRPasses() {
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if (TM->Options.ThreadModel == ThreadModel::Single)
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addPass(createLowerAtomicPass());
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else
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addPass(createAtomicExpandPass(TM));
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// Cmpxchg instructions are often used with a subsequent comparison to
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// determine whether it succeeded. We can exploit existing control-flow in
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// ldrex/strex loops to simplify this, but it needs tidying up.
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const ARMSubtarget *Subtarget = &getARMSubtarget();
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if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only())
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if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
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addPass(createCFGSimplificationPass());
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TargetPassConfig::addIRPasses();
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}
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bool ARMPassConfig::addPreISel() {
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if ((TM->getOptLevel() == CodeGenOpt::Aggressive &&
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EnableGlobalMerge == cl::BOU_UNSET) ||
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EnableGlobalMerge == cl::BOU_TRUE)
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// FIXME: This is using the thumb1 only constant value for
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// maximal global offset for merging globals. We may want
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// to look into using the old value for non-thumb1 code of
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// 4095 based on the TargetMachine, but this starts to become
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// tricky when doing code gen per function.
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addPass(createGlobalMergePass(TM, 127));
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return false;
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}
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bool ARMPassConfig::addInstSelector() {
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addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
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if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
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TM->Options.EnableFastISel)
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addPass(createARMGlobalBaseRegPass());
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return false;
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}
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void ARMPassConfig::addPreRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(createMLxExpansionPass());
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if (EnableARMLoadStoreOpt)
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addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
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if (!DisableA15SDOptimization)
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addPass(createA15SDOptimizerPass());
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}
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}
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void ARMPassConfig::addPreSched2() {
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if (getOptLevel() != CodeGenOpt::None) {
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if (EnableARMLoadStoreOpt)
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addPass(createARMLoadStoreOptimizationPass());
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addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
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}
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// Expand some pseudo instructions into multiple instructions to allow
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// proper scheduling.
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addPass(createARMExpandPseudoPass());
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if (getOptLevel() != CodeGenOpt::None) {
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// in v8, IfConversion depends on Thumb instruction widths
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if (getARMSubtarget().restrictIT())
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addPass(createThumb2SizeReductionPass());
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if (!getARMSubtarget().isThumb1Only())
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addPass(&IfConverterID);
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}
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addPass(createThumb2ITBlockPass());
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}
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void ARMPassConfig::addPreEmitPass() {
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addPass(createThumb2SizeReductionPass());
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// Constant island pass work on unbundled instructions.
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if (getARMSubtarget().isThumb2())
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addPass(&UnpackMachineBundlesID);
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addPass(createARMOptimizeBarriersPass());
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addPass(createARMConstantIslandPass());
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}
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