Akira Hatanaka db8e0bbedb [mips] Increase the number of floating point control registers available to 32. ... Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-01 20:31:44 +00:00
..
AArch64	AArch64: fix overzealous NEXTing for Windows testing.	2013-06-23 15:32:01 +00:00
ARM	ARM: Fix pseudo-instructions for SRS (Store Return State).	2013-06-28 15:09:46 +00:00
AsmParser
COFF
Disassembler	[mips] Increase the number of floating point control registers available to 32.	2013-07-01 20:31:44 +00:00
ELF	Added the test missed from r185080.	2013-07-01 09:02:33 +00:00
MachO
Markup
MBlaze
Mips	[mips] Do not emit ".option pic0" if target is mips64.	2013-06-26 19:08:49 +00:00
PowerPC	[PowerPC] Fix @got references to local symbols	2013-07-01 18:19:56 +00:00
SystemZ	[SystemZ] Immediate compare-and-branch support	2013-05-29 11:58:52 +00:00
X86	Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.	2013-06-18 17:08:10 +00:00