mirror of
https://github.com/c64scene-ar/llvm-6502.git
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057d0c3535
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56301 91177308-0d34-0410-b5e6-96231b3b80d8
577 lines
20 KiB
C++
577 lines
20 KiB
C++
//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the pass that transforms the ARM machine instructions into
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// relocatable machine code.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-emitter"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMInstrInfo.h"
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#include "ARMRelocations.h"
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#include "ARMSubtarget.h"
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#include "ARMTargetMachine.h"
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#include "llvm/Function.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineCodeEmitter.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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STATISTIC(NumEmitted, "Number of machine instructions emitted");
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namespace {
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class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
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ARMJITInfo *JTI;
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const ARMInstrInfo *II;
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const TargetData *TD;
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TargetMachine &TM;
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MachineCodeEmitter &MCE;
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const MachineConstantPool *MCP;
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public:
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static char ID;
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explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
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: MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
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MCE(mce), MCP(0) {}
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ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
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const ARMInstrInfo &ii, const TargetData &td)
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: MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
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MCE(mce), MCP(0) {}
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bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "ARM Machine Code Emitter";
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}
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void emitInstruction(const MachineInstr &MI);
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private:
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void emitConstPoolInstruction(const MachineInstr &MI);
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void emitPseudoInstruction(const MachineInstr &MI);
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unsigned getAddrModeNoneInstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary);
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unsigned getMachineSoRegOpValue(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned OpIdx);
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unsigned getAddrMode1SBit(const MachineInstr &MI,
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const TargetInstrDesc &TID) const;
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unsigned getAddrMode1InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary);
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unsigned getAddrMode2InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary);
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unsigned getAddrMode3InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary);
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unsigned getAddrMode4InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary);
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/// getInstrBinary - Return binary encoding for the specified
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/// machine instruction.
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unsigned getInstrBinary(const MachineInstr &MI);
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/// getBinaryCodeForInstr - This function, generated by the
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/// CodeEmitterGenerator using TableGen, produces the binary encoding for
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/// machine instructions.
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///
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unsigned getBinaryCodeForInstr(const MachineInstr &MI);
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
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return getMachineOpValue(MI, MI.getOperand(OpIdx));
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}
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unsigned getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO);
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/// getBaseOpcodeFor - Return the opcode value.
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///
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unsigned getBaseOpcodeFor(const TargetInstrDesc &TID) const {
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return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
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}
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/// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
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///
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unsigned getShiftOp(const MachineOperand &MO) const ;
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/// Routines that handle operands which add machine relocations which are
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/// fixed up by the JIT fixup stage.
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void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
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bool DoesntNeedStub);
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void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
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void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
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int Disp = 0, unsigned PCAdj = 0 );
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void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
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unsigned PCAdj = 0);
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void emitGlobalConstant(const Constant *CV);
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void emitMachineBasicBlock(MachineBasicBlock *BB);
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};
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char ARMCodeEmitter::ID = 0;
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}
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/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
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/// to the specified MCE object.
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FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
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MachineCodeEmitter &MCE) {
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return new ARMCodeEmitter(TM, MCE);
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}
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bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
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MF.getTarget().getRelocationModel() != Reloc::Static) &&
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"JIT relocation model must be set to static or default!");
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II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
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TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
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JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
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MCP = MF.getConstantPool();
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do {
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DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
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MCE.startFunction(MF);
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for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
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MBB != E; ++MBB) {
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MCE.StartMachineBasicBlock(MBB);
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for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I)
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emitInstruction(*I);
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}
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} while (MCE.finishFunction(MF));
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return false;
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}
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/// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
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///
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unsigned ARMCodeEmitter::getShiftOp(const MachineOperand &MO) const {
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switch (ARM_AM::getAM2ShiftOpc(MO.getImm())) {
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default: assert(0 && "Unknown shift opc!");
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case ARM_AM::asr: return 2;
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case ARM_AM::lsl: return 0;
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case ARM_AM::lsr: return 1;
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case ARM_AM::ror:
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case ARM_AM::rrx: return 3;
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}
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return 0;
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}
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) {
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if (MO.isRegister())
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return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
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else if (MO.isImmediate())
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return static_cast<unsigned>(MO.getImm());
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else if (MO.isGlobalAddress())
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emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, false);
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else if (MO.isExternalSymbol())
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emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
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else if (MO.isConstantPoolIndex())
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emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
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else if (MO.isJumpTableIndex())
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emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
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else if (MO.isMachineBasicBlock())
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emitMachineBasicBlock(MO.getMBB());
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else {
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cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
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abort();
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}
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return 0;
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}
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/// emitGlobalAddress - Emit the specified address to the code stream.
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///
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void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV,
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unsigned Reloc, bool DoesntNeedStub) {
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MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
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Reloc, GV, 0, DoesntNeedStub));
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}
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/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
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MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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Reloc, ES));
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}
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/// emitConstPoolAddress - Arrange for the address of an constant pool
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/// to be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
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int Disp /* = 0 */,
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unsigned PCAdj /* = 0 */) {
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MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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Reloc, CPI, PCAdj));
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}
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/// emitJumpTableAddress - Arrange for the address of a jump table to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
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unsigned PCAdj /* = 0 */) {
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MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
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Reloc, JTIndex, PCAdj));
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}
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/// emitMachineBasicBlock - Emit the specified address basic block.
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void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
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MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
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ARM::reloc_arm_branch, BB));
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}
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void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
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DOUT << MI;
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NumEmitted++; // Keep track of the # of mi's emitted
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if ((MI.getDesc().TSFlags & ARMII::FormMask) == ARMII::Pseudo)
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emitPseudoInstruction(MI);
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else
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MCE.emitWordLE(getInstrBinary(MI));
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}
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unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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// FIXME: Assume CC is AL for now.
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Binary |= ARMCC::AL << 28;
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switch (TID.TSFlags & ARMII::FormMask) {
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default:
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assert(0 && "Unknown instruction subtype!");
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break;
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case ARMII::Branch: {
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// Set signed_immed_24 field
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Binary |= getMachineOpValue(MI, 0);
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// if it is a conditional branch, set cond field
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if (TID.Opcode == ARM::Bcc) {
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Binary &= 0x0FFFFFFF; // clear conditional field
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Binary |= getMachineOpValue(MI, 1) << 28; // set conditional field
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}
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break;
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}
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case ARMII::BranchMisc: {
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if (TID.Opcode == ARM::BX)
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abort(); // FIXME
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if (TID.Opcode == ARM::BX_RET)
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Binary |= 0xe; // the return register is LR
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else
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// otherwise, set the return register
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Binary |= getMachineOpValue(MI, 0);
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break;
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}
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}
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return Binary;
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}
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unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned OpIdx) {
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// Set last operand (register Rm)
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unsigned Binary = getMachineOpValue(MI, OpIdx);
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const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
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const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
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ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
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// Encode the shift opcode.
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unsigned SBits = 0;
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unsigned Rs = MO1.getReg();
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if (Rs) {
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// Set shift operand (bit[7:4]).
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// LSL - 0001
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// LSR - 0011
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// ASR - 0101
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// ROR - 0111
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// RRX - 0110 and bit[11:8] clear.
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switch (SOpc) {
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default: assert(0 && "Unknown shift opc!");
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case ARM_AM::lsl: SBits = 0x1; break;
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case ARM_AM::lsr: SBits = 0x3; break;
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case ARM_AM::asr: SBits = 0x5; break;
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case ARM_AM::ror: SBits = 0x7; break;
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case ARM_AM::rrx: SBits = 0x6; break;
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}
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} else {
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// Set shift operand (bit[6:4]).
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// LSL - 000
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// LSR - 010
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// ASR - 100
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// ROR - 110
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switch (SOpc) {
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default: assert(0 && "Unknown shift opc!");
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case ARM_AM::lsl: SBits = 0x0; break;
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case ARM_AM::lsr: SBits = 0x2; break;
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case ARM_AM::asr: SBits = 0x4; break;
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case ARM_AM::ror: SBits = 0x6; break;
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}
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}
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Binary |= SBits << 4;
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if (SOpc == ARM_AM::rrx)
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return Binary;
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// Encode the shift operation Rs or shift_imm (except rrx).
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if (Rs) {
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// Encode Rs bit[11:8].
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assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
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return Binary |
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(ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
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}
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// Encode shift_imm bit[11:7].
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return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
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}
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unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
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const TargetInstrDesc &TID) const {
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for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
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const MachineOperand &MO = MI.getOperand(i-1);
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if (MO.isRegister() && MO.isDef() && MO.getReg() == ARM::CPSR)
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return 1 << ARMII::S_BitShift;
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}
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return 0;
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}
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void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
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// FIXME
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}
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void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
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unsigned Opcode = MI.getDesc().Opcode;
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switch (Opcode) {
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default:
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abort(); // FIXME:
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case ARM::CONSTPOOL_ENTRY: {
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emitConstPoolInstruction(MI);
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break;
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}
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}
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}
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unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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// FIXME: Assume CC is AL for now.
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Binary |= ARMCC::AL << 28;
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// Encode S bit if MI modifies CPSR.
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Binary |= getAddrMode1SBit(MI, TID);
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// Encode register def if there is one.
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unsigned NumDefs = TID.getNumDefs();
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unsigned OpIdx = 0;
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if (NumDefs) {
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdShift;
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++OpIdx;
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}
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// Encode first non-shifter register operand if ther is one.
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unsigned Format = TID.TSFlags & ARMII::FormMask;
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bool isUnary = (Format == ARMII::DPRdMisc ||
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Format == ARMII::DPRdIm ||
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Format == ARMII::DPRdReg ||
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Format == ARMII::DPRdSoReg ||
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Format == ARMII::DPRnIm ||
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Format == ARMII::DPRnReg ||
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Format == ARMII::DPRnSoReg);
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if (!isUnary) {
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
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++OpIdx;
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}
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// Encode shifter operand.
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bool HasSoReg = (Format == ARMII::DPRdSoReg ||
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Format == ARMII::DPRnSoReg ||
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Format == ARMII::DPRSoReg ||
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Format == ARMII::DPRSoRegS);
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if (HasSoReg)
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// Encode SoReg.
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return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
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const MachineOperand &MO = MI.getOperand(OpIdx);
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if (MO.isRegister())
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// Encode register Rm.
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return Binary | getMachineOpValue(MI, NumDefs + 1);
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// Encode so_imm.
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// Set bit I(25) to identify this is the immediate form of <shifter_op>
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Binary |= 1 << ARMII::I_BitShift;
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unsigned SoImm = MO.getImm();
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// Encode rotate_imm.
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Binary |= ARM_AM::getSOImmValRot(SoImm) << ARMII::RotImmShift;
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// Encode immed_8.
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Binary |= ARM_AM::getSOImmVal(SoImm);
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return Binary;
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}
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unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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// FIXME: Assume CC is AL for now.
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Binary |= ARMCC::AL << 28;
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// Set first operand
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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// Set second operand
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Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
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const MachineOperand &MO2 = MI.getOperand(2);
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const MachineOperand &MO3 = MI.getOperand(3);
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// Set bit U(23) according to sign of immed value (positive or negative).
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Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
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ARMII::U_BitShift);
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if (!MO2.getReg()) { // is immediate
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if (ARM_AM::getAM2Offset(MO3.getImm()))
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// Set the value of offset_12 field
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Binary |= ARM_AM::getAM2Offset(MO3.getImm());
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return Binary;
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}
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// Set bit I(25), because this is not in immediate enconding.
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Binary |= 1 << ARMII::I_BitShift;
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assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
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// Set bit[3:0] to the corresponding Rm register
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Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
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// if this instr is in scaled register offset/index instruction, set
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// shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
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Binary |= getShiftOp(MO3) << 5; // shift
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Binary |= ShImm << 7; // shift_immed
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}
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return Binary;
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}
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unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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// FIXME: Assume CC is AL for now.
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Binary |= ARMCC::AL << 28;
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|
|
|
// Set first operand
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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|
|
|
// Set second operand
|
|
Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
|
|
|
|
const MachineOperand &MO2 = MI.getOperand(2);
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|
const MachineOperand &MO3 = MI.getOperand(3);
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|
|
|
// Set bit U(23) according to sign of immed value (positive or negative)
|
|
Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
|
|
ARMII::U_BitShift);
|
|
|
|
// If this instr is in register offset/index encoding, set bit[3:0]
|
|
// to the corresponding Rm register.
|
|
if (MO2.getReg()) {
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|
Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
|
|
return Binary;
|
|
}
|
|
|
|
// if this instr is in immediate offset/index encoding, set bit 22 to 1
|
|
if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
|
|
Binary |= 1 << 22;
|
|
// Set operands
|
|
Binary |= (ImmOffs >> 4) << 8; // immedH
|
|
Binary |= (ImmOffs & ~0xF); // immedL
|
|
}
|
|
|
|
return Binary;
|
|
}
|
|
|
|
unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
|
|
const TargetInstrDesc &TID,
|
|
unsigned Binary) {
|
|
// FIXME: Assume CC is AL for now.
|
|
Binary |= ARMCC::AL << 28;
|
|
|
|
// Set first operand
|
|
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
|
|
|
|
// Set addressing mode by modifying bits U(23) and P(24)
|
|
// IA - Increment after - bit U = 1 and bit P = 0
|
|
// IB - Increment before - bit U = 1 and bit P = 1
|
|
// DA - Decrement after - bit U = 0 and bit P = 0
|
|
// DB - Decrement before - bit U = 0 and bit P = 1
|
|
const MachineOperand &MO = MI.getOperand(1);
|
|
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
|
|
switch (Mode) {
|
|
default: assert(0 && "Unknown addressing sub-mode!");
|
|
case ARM_AM::da: break;
|
|
case ARM_AM::db: Binary |= 0x1 << 24; break;
|
|
case ARM_AM::ia: Binary |= 0x1 << 23; break;
|
|
case ARM_AM::ib: Binary |= 0x3 << 23; break;
|
|
}
|
|
|
|
// Set bit W(21)
|
|
if (ARM_AM::getAM4WBFlag(MO.getImm()))
|
|
Binary |= 0x1 << 21;
|
|
|
|
// Set registers
|
|
for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI.getOperand(i);
|
|
if (MO.isRegister() && MO.isImplicit())
|
|
continue;
|
|
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
|
|
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
|
|
RegNum < 16);
|
|
Binary |= 0x1 << RegNum;
|
|
}
|
|
|
|
return Binary;
|
|
}
|
|
|
|
/// getInstrBinary - Return binary encoding for the specified
|
|
/// machine instruction.
|
|
unsigned ARMCodeEmitter::getInstrBinary(const MachineInstr &MI) {
|
|
// Part of binary is determined by TableGn.
|
|
unsigned Binary = getBinaryCodeForInstr(MI);
|
|
|
|
const TargetInstrDesc &TID = MI.getDesc();
|
|
switch (TID.TSFlags & ARMII::AddrModeMask) {
|
|
case ARMII::AddrModeNone:
|
|
return getAddrModeNoneInstrBinary(MI, TID, Binary);
|
|
case ARMII::AddrMode1:
|
|
return getAddrMode1InstrBinary(MI, TID, Binary);
|
|
case ARMII::AddrMode2:
|
|
return getAddrMode2InstrBinary(MI, TID, Binary);
|
|
case ARMII::AddrMode3:
|
|
return getAddrMode3InstrBinary(MI, TID, Binary);
|
|
case ARMII::AddrMode4:
|
|
return getAddrMode4InstrBinary(MI, TID, Binary);
|
|
}
|
|
|
|
abort();
|
|
return 0;
|
|
}
|
|
|
|
#include "ARMGenCodeEmitter.inc"
|