llvm-6502/test/CodeGen
Chad Rosier abd6674166 Fix a regression from r147481.
Original commit message from r147481:
DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.

Fix:
Unaligned loads need to generate a vmovups.
rdar://10974078



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 02:00:48 +00:00
..
ARM Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation). 2012-03-06 23:33:32 +00:00
CBackend
CellSPU
CPP
Generic
Hexagon
MBlaze
Mips Remove the no longer existent psp triple from a test. 2012-03-08 21:22:27 +00:00
MSP430
PowerPC
PTX
SPARC
Thumb
Thumb2
X86 Fix a regression from r147481. 2012-03-09 02:00:48 +00:00
XCore