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https://github.com/c64scene-ar/llvm-6502.git
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4a92638aec
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193309 91177308-0d34-0410-b5e6-96231b3b80d8
309 lines
10 KiB
LLVM
309 lines
10 KiB
LLVM
; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse | FileCheck %s
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define <4 x float> @test_x86_sse_add_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: addss
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%res = call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.add.ss(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_cmp_ps(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: cmpordps
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%res = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
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define <4 x float> @test_x86_sse_cmp_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: cmpordss
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%res = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8) nounwind readnone
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define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: comiss
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; CHECK: sete
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; CHECK: movzbl
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%res = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: comiss
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; CHECK: setae
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; CHECK: movzbl
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%res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.comige.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: comiss
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; CHECK: seta
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; CHECK: movzbl
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%res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.comigt.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: comiss
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; CHECK: setbe
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; CHECK: movzbl
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%res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.comile.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: comiss
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; CHECK: sbb
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%res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.comilt.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: comiss
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; CHECK: setne
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; CHECK: movzbl
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%res = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.comineq.ss(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_cvtsi2ss(<4 x float> %a0) {
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; CHECK: movl
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; CHECK: cvtsi2ss
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%res = call <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float> %a0, i32 7) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float>, i32) nounwind readnone
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define i32 @test_x86_sse_cvtss2si(<4 x float> %a0) {
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; CHECK: cvtss2si
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%res = call i32 @llvm.x86.sse.cvtss2si(<4 x float> %a0) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.cvtss2si(<4 x float>) nounwind readnone
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define i32 @test_x86_sse_cvttss2si(<4 x float> %a0) {
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; CHECK: cvttss2si
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%res = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_div_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: divss
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%res = call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.div.ss(<4 x float>, <4 x float>) nounwind readnone
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define void @test_x86_sse_ldmxcsr(i8* %a0) {
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; CHECK: movl
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; CHECK: ldmxcsr
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call void @llvm.x86.sse.ldmxcsr(i8* %a0)
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ret void
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}
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declare void @llvm.x86.sse.ldmxcsr(i8*) nounwind
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define <4 x float> @test_x86_sse_max_ps(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: maxps
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%res = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_max_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: maxss
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%res = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_min_ps(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: minps
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%res = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_min_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: minss
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%res = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_movmsk_ps(<4 x float> %a0) {
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; CHECK: movmskps
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%res = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %a0) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_mul_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: mulss
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%res = call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_rcp_ps(<4 x float> %a0) {
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; CHECK: rcpps
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%res = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_rcp_ss(<4 x float> %a0) {
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; CHECK: rcpss
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%res = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_rsqrt_ps(<4 x float> %a0) {
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; CHECK: rsqrtps
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%res = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_rsqrt_ss(<4 x float> %a0) {
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; CHECK: rsqrtss
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%res = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_sqrt_ps(<4 x float> %a0) {
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; CHECK: sqrtps
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%res = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_sqrt_ss(<4 x float> %a0) {
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; CHECK: sqrtss
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%res = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
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define void @test_x86_sse_stmxcsr(i8* %a0) {
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; CHECK: movl
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; CHECK: stmxcsr
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call void @llvm.x86.sse.stmxcsr(i8* %a0)
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ret void
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}
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declare void @llvm.x86.sse.stmxcsr(i8*) nounwind
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define void @test_x86_sse_storeu_ps(i8* %a0, <4 x float> %a1) {
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; CHECK: movl
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; CHECK: movups
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call void @llvm.x86.sse.storeu.ps(i8* %a0, <4 x float> %a1)
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ret void
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}
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declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind
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define <4 x float> @test_x86_sse_sub_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: subss
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%res = call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: ucomiss
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; CHECK: sete
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; CHECK: movzbl
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%res = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: ucomiss
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; CHECK: setae
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; CHECK: movzbl
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%res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: ucomiss
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; CHECK: seta
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; CHECK: movzbl
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%res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.ucomigt.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: ucomiss
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; CHECK: setbe
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; CHECK: movzbl
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%res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.ucomile.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: ucomiss
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; CHECK: sbbl
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%res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.ucomilt.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: ucomiss
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; CHECK: setne
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; CHECK: movzbl
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%res = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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declare i32 @llvm.x86.sse.ucomineq.ss(<4 x float>, <4 x float>) nounwind readnone
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