mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
93 lines
4.3 KiB
LLVM
93 lines
4.3 KiB
LLVM
; RUN: llc %s -o - -mattr=+avx | FileCheck %s
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx"
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; For this test we used to optimize the <i1 true, i1 false, i1 false, i1 true>
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; mask into <i32 2147483648, i32 0, i32 0, i32 2147483648> because we thought
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; we would lower that into a blend where only the high bit is relevant.
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; However, since the whole mask is constant, this is simplified incorrectly
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; by the generic code, because it was expecting -1 in place of 2147483648.
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;
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; The problem does not occur without AVX, because vselect of v4i32 is not legal
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; nor custom.
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;
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; <rdar://problem/18675020>
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; CHECK-LABEL: test:
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; CHECK: vmovdqa {{.*#+}} xmm0 = [65535,0,0,65535]
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; CHECK: vmovdqa {{.*#+}} xmm2 = [65533,124,125,14807]
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; CHECK: ret
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define void @test(<4 x i16>* %a, <4 x i16>* %b) {
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body:
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%predphi = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> <i16 -3, i16 545, i16 4385, i16 14807>, <4 x i16> <i16 123, i16 124, i16 125, i16 127>
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%predphi42 = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> zeroinitializer
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store <4 x i16> %predphi, <4 x i16>* %a, align 8
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store <4 x i16> %predphi42, <4 x i16>* %b, align 8
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ret void
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}
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; Improve code coverage.
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;
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; When shrinking the condition used into the select to match a blend, this
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; test case exercises the path where the modified node is not the root
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; of the condition.
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;
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; CHECK-LABEL: test2:
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; CHECK: vpslld $31, %xmm0, %xmm0
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; CHECK-NEXT: vpmovsxdq %xmm0, %xmm1
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; CHECK-NEXT: vpshufd $78, %xmm0, %xmm0 ## xmm0 = xmm0[2,3,0,1]
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; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, [[MASK:%ymm[0-9]+]]
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; CHECK: vblendvpd [[MASK]]
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; CHECK: retq
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define void @test2(double** %call1559, i64 %indvars.iv4198, <4 x i1> %tmp1895) {
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bb:
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%arrayidx1928 = getelementptr inbounds double*, double** %call1559, i64 %indvars.iv4198
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%tmp1888 = load double*, double** %arrayidx1928, align 8
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%predphi.v.v = select <4 x i1> %tmp1895, <4 x double> <double -5.000000e-01, double -5.000000e-01, double -5.000000e-01, double -5.000000e-01>, <4 x double> <double 5.000000e-01, double 5.000000e-01, double 5.000000e-01, double 5.000000e-01>
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%tmp1900 = bitcast double* %tmp1888 to <4 x double>*
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store <4 x double> %predphi.v.v, <4 x double>* %tmp1900, align 8
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ret void
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}
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; For this test, we used to optimized the conditional mask for the blend, i.e.,
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; we shrunk some of its bits.
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; However, this same mask was used in another select (%predphi31) that turned out
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; to be optimized into a and. In that case, the conditional mask was wrong.
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;
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; Make sure that the and is fed by the original mask.
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;
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; <rdar://problem/18819506>
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; CHECK-LABEL: test3:
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; Compute the mask.
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; CHECK: vpcmpeqd {{%xmm[0-9]+}}, {{%xmm[0-9]+}}, [[MASK:%xmm[0-9]+]]
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; Do not shrink the bit of the mask.
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; CHECK-NOT: vpslld $31, [[MASK]], {{%xmm[0-9]+}}
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; Use the mask in the blend.
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; CHECK-NEXT: vblendvps [[MASK]], %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
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; Use the mask in the and.
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; CHECK-NEXT: vpand LCPI2_2(%rip), [[MASK]], {{%xmm[0-9]+}}
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; CHECK: retq
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define void @test3(<4 x i32> %induction30, <4 x i16>* %tmp16, <4 x i16>* %tmp17, <4 x i16> %tmp3, <4 x i16> %tmp12) {
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%tmp6 = srem <4 x i32> %induction30, <i32 3, i32 3, i32 3, i32 3>
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%tmp7 = icmp eq <4 x i32> %tmp6, zeroinitializer
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%predphi = select <4 x i1> %tmp7, <4 x i16> %tmp3, <4 x i16> %tmp12
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%predphi31 = select <4 x i1> %tmp7, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> zeroinitializer
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store <4 x i16> %predphi31, <4 x i16>* %tmp16, align 8
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store <4 x i16> %predphi, <4 x i16>* %tmp17, align 8
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ret void
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}
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; We shouldn't try to lower this directly using VSELECT because we don't have
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; vpblendvb in AVX1, only in AVX2. Instead, it should be expanded.
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;
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; CHECK-LABEL: PR22706:
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; CHECK: vpcmpgtb
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; CHECK: vpcmpgtb
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define <32 x i8> @PR22706(<32 x i1> %x) {
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%tmp = select <32 x i1> %x, <32 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <32 x i8> <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
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ret <32 x i8> %tmp
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}
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