Duncan Sands c69d74a5d4 Revert commit 80428. It completely broke exception ... handling on x86-32 linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80592 91177308-0d34-0410-b5e6-96231b3b80d8		2009-08-31 16:45:16 +00:00
..
SubtargetFeature.h	Switch SubtargetFeature off of ostreams	2009-08-23 21:41:43 +00:00
Target.td
TargetAsmParser.h
TargetCallingConv.td
TargetData.h	Try again at privatizing the layout info map, with a rewritten patch.	2009-08-21 19:59:12 +00:00
TargetELFWriterInfo.h
TargetFrameInfo.h
TargetInstrDesc.h
TargetInstrInfo.h	rename TAI -> MAI, being careful not to make MAILJMP instructions :)	2009-08-22 21:43:10 +00:00
TargetInstrItineraries.h	Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.	2009-08-19 16:08:58 +00:00
TargetIntrinsicInfo.h
TargetJITInfo.h
TargetLowering.h	Revert commit 80428. It completely broke exception	2009-08-31 16:45:16 +00:00
TargetLoweringObjectFile.h	Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.	2009-08-22 20:48:53 +00:00
TargetMachine.h	Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.	2009-08-22 20:48:53 +00:00
TargetMachOWriterInfo.h
TargetOptions.h
TargetRegisterInfo.h
TargetRegistry.h	llvm-mc: Tweak MCCodeEmitter skeleton.	2009-08-27 01:34:22 +00:00
TargetSchedule.td	Extend the instruction itinerary model to include the ability to indicate the def and use cycle for each operand. This additional information is optional, so existing itineraries do not need to be changed.	2009-08-17 16:02:57 +00:00
TargetSelect.h
TargetSelectionDAG.td	Add a new "SDTCisVec" SDTypeConstraint. This complements the vAny type.	2009-08-12 22:30:59 +00:00
TargetSubtarget.h	Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.	2009-08-19 16:08:58 +00:00