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https://github.com/c64scene-ar/llvm-6502.git
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5d6365c80c
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216225 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
947 B
LLVM
41 lines
947 B
LLVM
; RUN: llc -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=aarch64 < %s | FileCheck %s
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@var8 = global i8 0
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@var16 = global i16 0
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@var32 = global i32 0
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@var64 = global i64 0
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define void @test_mul8(i8 %lhs, i8 %rhs) {
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; CHECK-LABEL: test_mul8:
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; CHECK: mul {{w[0-9]+}}, w0, w1
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; %lhs = load i8* @var8
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; %rhs = load i8* @var8
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%prod = mul i8 %lhs, %rhs
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store i8 %prod, i8* @var8
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ret void
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}
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define void @test_mul16(i16 %lhs, i16 %rhs) {
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; CHECK-LABEL: test_mul16:
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; CHECK: mul {{w[0-9]+}}, w0, w1
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%prod = mul i16 %lhs, %rhs
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store i16 %prod, i16* @var16
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ret void
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}
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define void @test_mul32(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: test_mul32:
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; CHECK: mul {{w[0-9]+}}, w0, w1
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%prod = mul i32 %lhs, %rhs
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store i32 %prod, i32* @var32
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ret void
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}
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define void @test_mul64(i64 %lhs, i64 %rhs) {
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; CHECK-LABEL: test_mul64:
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; CHECK: mul {{x[0-9]+}}, x0, x1
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%prod = mul i64 %lhs, %rhs
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store i64 %prod, i64* @var64
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ret void
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}
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