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bc0bdb26da
In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195980 91177308-0d34-0410-b5e6-96231b3b80d8
97 lines
5.3 KiB
TableGen
97 lines
5.3 KiB
TableGen
//===-- PPCScheduleG4.td - PPC G4 Scheduling Definitions ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the G4 (7400) processor.
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//
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//===----------------------------------------------------------------------===//
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def G4_BPU : FuncUnit; // Branch unit
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def G4_SLU : FuncUnit; // Store/load unit
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def G4_SRU : FuncUnit; // special register unit
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def G4_IU1 : FuncUnit; // integer unit 1 (simple)
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def G4_IU2 : FuncUnit; // integer unit 2 (complex)
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def G4_FPU1 : FuncUnit; // floating point unit 1
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def G4_VPU : FuncUnit; // vector permutation unit
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def G4_VIU1 : FuncUnit; // vector integer unit 1 (simple)
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def G4_VIU2 : FuncUnit; // vector integer unit 2 (complex)
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def G4_VFPU : FuncUnit; // vector floating point unit
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def G4Itineraries : ProcessorItineraries<
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[G4_IU1, G4_IU2, G4_SLU, G4_SRU, G4_BPU, G4_FPU1,
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G4_VIU1, G4_VIU2, G4_VPU, G4_VFPU], [], [
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InstrItinData<IIC_IntSimple , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
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InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
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InstrItinData<IIC_IntCompare , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
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InstrItinData<IIC_IntDivW , [InstrStage<19, [G4_IU1]>]>,
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InstrItinData<IIC_IntMFFS , [InstrStage<3, [G4_FPU1]>]>,
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InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G4_VIU1]>]>,
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InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G4_FPU1]>]>,
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InstrItinData<IIC_IntMulHW , [InstrStage<5, [G4_IU1]>]>,
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InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G4_IU1]>]>,
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InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4_IU1]>]>,
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InstrItinData<IIC_IntRotate , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
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InstrItinData<IIC_IntShift , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
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InstrItinData<IIC_IntTrapW , [InstrStage<2, [G4_IU1, G4_IU2]>]>,
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InstrItinData<IIC_BrB , [InstrStage<1, [G4_BPU]>]>,
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InstrItinData<IIC_BrCR , [InstrStage<1, [G4_SRU]>]>,
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InstrItinData<IIC_BrMCR , [InstrStage<1, [G4_SRU]>]>,
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InstrItinData<IIC_BrMCRX , [InstrStage<1, [G4_SRU]>]>,
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InstrItinData<IIC_LdStDCBF , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStDCBI , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStLoad , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStLoadUpdX, [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStStore , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStDSS , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStICBI , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStSTFD , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStLFD , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStLFDU , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStLFDUX , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStLHA , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStLHAU , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStLHAUX , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStLMW , [InstrStage<34, [G4_SLU]>]>,
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InstrItinData<IIC_LdStLVecX , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G4_SLU]>]>,
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InstrItinData<IIC_LdStSTVEBX , [InstrStage<2, [G4_SLU]>]>,
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InstrItinData<IIC_LdStSTWCX , [InstrStage<5, [G4_SLU]>]>,
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InstrItinData<IIC_LdStSync , [InstrStage<8, [G4_SLU]>]>,
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InstrItinData<IIC_SprISYNC , [InstrStage<2, [G4_SRU]>]>,
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InstrItinData<IIC_SprMFSR , [InstrStage<3, [G4_SRU]>]>,
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InstrItinData<IIC_SprMTMSR , [InstrStage<1, [G4_SRU]>]>,
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InstrItinData<IIC_SprMTSR , [InstrStage<2, [G4_SRU]>]>,
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InstrItinData<IIC_SprTLBSYNC , [InstrStage<8, [G4_SRU]>]>,
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InstrItinData<IIC_SprMFCR , [InstrStage<1, [G4_SRU]>]>,
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InstrItinData<IIC_SprMFMSR , [InstrStage<1, [G4_SRU]>]>,
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InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G4_SRU]>]>,
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InstrItinData<IIC_SprMFTB , [InstrStage<1, [G4_SRU]>]>,
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InstrItinData<IIC_SprMTSPR , [InstrStage<2, [G4_SRU]>]>,
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InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [G4_SRU]>]>,
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InstrItinData<IIC_SprRFI , [InstrStage<2, [G4_SRU]>]>,
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InstrItinData<IIC_SprSC , [InstrStage<2, [G4_SRU]>]>,
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InstrItinData<IIC_FPGeneral , [InstrStage<1, [G4_FPU1]>]>,
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InstrItinData<IIC_FPAddSub , [InstrStage<1, [G4_FPU1]>]>,
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InstrItinData<IIC_FPCompare , [InstrStage<1, [G4_FPU1]>]>,
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InstrItinData<IIC_FPDivD , [InstrStage<31, [G4_FPU1]>]>,
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InstrItinData<IIC_FPDivS , [InstrStage<17, [G4_FPU1]>]>,
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InstrItinData<IIC_FPFused , [InstrStage<1, [G4_FPU1]>]>,
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InstrItinData<IIC_FPRes , [InstrStage<10, [G4_FPU1]>]>,
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InstrItinData<IIC_VecGeneral , [InstrStage<1, [G4_VIU1]>]>,
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InstrItinData<IIC_VecFP , [InstrStage<4, [G4_VFPU]>]>,
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InstrItinData<IIC_VecFPCompare, [InstrStage<1, [G4_VIU1]>]>,
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InstrItinData<IIC_VecComplex , [InstrStage<3, [G4_VIU2]>]>,
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InstrItinData<IIC_VecPerm , [InstrStage<1, [G4_VPU]>]>,
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InstrItinData<IIC_VecFPRound , [InstrStage<4, [G4_VFPU]>]>,
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InstrItinData<IIC_VecVSL , [InstrStage<1, [G4_VIU1]>]>,
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InstrItinData<IIC_VecVSR , [InstrStage<1, [G4_VIU1]>]>
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]>;
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