mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
26d628d6ce
Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230775 91177308-0d34-0410-b5e6-96231b3b80d8
628 lines
16 KiB
LLVM
628 lines
16 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
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; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
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; Load / Store Base Register only
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define zeroext i1 @load_breg_i1(i1* %a) {
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; CHECK-LABEL: load_breg_i1
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; CHECK: ldrb {{w[0-9]+}}, [x0]
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%1 = load i1* %a
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ret i1 %1
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}
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define zeroext i8 @load_breg_i8(i8* %a) {
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; CHECK-LABEL: load_breg_i8
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; CHECK: ldrb {{w[0-9]+}}, [x0]
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%1 = load i8* %a
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ret i8 %1
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}
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define zeroext i16 @load_breg_i16(i16* %a) {
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; CHECK-LABEL: load_breg_i16
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; CHECK: ldrh {{w[0-9]+}}, [x0]
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%1 = load i16* %a
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ret i16 %1
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}
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define i32 @load_breg_i32(i32* %a) {
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; CHECK-LABEL: load_breg_i32
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; CHECK: ldr {{w[0-9]+}}, [x0]
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%1 = load i32* %a
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ret i32 %1
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}
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define i64 @load_breg_i64(i64* %a) {
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; CHECK-LABEL: load_breg_i64
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; CHECK: ldr {{x[0-9]+}}, [x0]
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%1 = load i64* %a
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ret i64 %1
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}
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define float @load_breg_f32(float* %a) {
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; CHECK-LABEL: load_breg_f32
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; CHECK: ldr {{s[0-9]+}}, [x0]
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%1 = load float* %a
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ret float %1
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}
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define double @load_breg_f64(double* %a) {
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; CHECK-LABEL: load_breg_f64
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; CHECK: ldr {{d[0-9]+}}, [x0]
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%1 = load double* %a
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ret double %1
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}
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define void @store_breg_i1(i1* %a) {
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; CHECK-LABEL: store_breg_i1
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; CHECK: strb wzr, [x0]
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store i1 0, i1* %a
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ret void
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}
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define void @store_breg_i1_2(i1* %a) {
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; CHECK-LABEL: store_breg_i1_2
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; CHECK: strb {{w[0-9]+}}, [x0]
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store i1 true, i1* %a
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ret void
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}
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define void @store_breg_i8(i8* %a) {
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; CHECK-LABEL: store_breg_i8
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; CHECK: strb wzr, [x0]
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store i8 0, i8* %a
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ret void
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}
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define void @store_breg_i16(i16* %a) {
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; CHECK-LABEL: store_breg_i16
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; CHECK: strh wzr, [x0]
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store i16 0, i16* %a
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ret void
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}
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define void @store_breg_i32(i32* %a) {
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; CHECK-LABEL: store_breg_i32
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; CHECK: str wzr, [x0]
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store i32 0, i32* %a
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ret void
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}
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define void @store_breg_i64(i64* %a) {
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; CHECK-LABEL: store_breg_i64
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; CHECK: str xzr, [x0]
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store i64 0, i64* %a
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ret void
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}
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define void @store_breg_f32(float* %a) {
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; CHECK-LABEL: store_breg_f32
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; CHECK: str wzr, [x0]
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store float 0.0, float* %a
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ret void
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}
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define void @store_breg_f64(double* %a) {
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; CHECK-LABEL: store_breg_f64
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; CHECK: str xzr, [x0]
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store double 0.0, double* %a
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ret void
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}
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; Load Immediate
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define i32 @load_immoff_1() {
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; CHECK-LABEL: load_immoff_1
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; CHECK: orr {{w|x}}[[REG:[0-9]+]], {{wzr|xzr}}, #0x80
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; CHECK: ldr {{w[0-9]+}}, {{\[}}x[[REG]]{{\]}}
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%1 = inttoptr i64 128 to i32*
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%2 = load i32* %1
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ret i32 %2
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}
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; Load / Store Base Register + Immediate Offset
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; Max supported negative offset
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define i32 @load_breg_immoff_1(i64 %a) {
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; CHECK-LABEL: load_breg_immoff_1
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; CHECK: ldur {{w[0-9]+}}, [x0, #-256]
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%1 = add i64 %a, -256
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32* %2
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ret i32 %3
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}
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; Min not-supported negative offset
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define i32 @load_breg_immoff_2(i64 %a) {
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; CHECK-LABEL: load_breg_immoff_2
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; CHECK: sub [[REG:x[0-9]+]], x0, #257
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; CHECK-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, -257
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32* %2
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ret i32 %3
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}
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; Max supported unscaled offset
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define i32 @load_breg_immoff_3(i64 %a) {
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; CHECK-LABEL: load_breg_immoff_3
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; CHECK: ldur {{w[0-9]+}}, [x0, #255]
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%1 = add i64 %a, 255
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32* %2
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ret i32 %3
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}
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; Min un-supported unscaled offset
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define i32 @load_breg_immoff_4(i64 %a) {
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; CHECK-LABEL: load_breg_immoff_4
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; CHECK: add [[REG:x[0-9]+]], x0, #257
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; CHECK-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, 257
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32* %2
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ret i32 %3
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}
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; Max supported scaled offset
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define i32 @load_breg_immoff_5(i64 %a) {
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; CHECK-LABEL: load_breg_immoff_5
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; CHECK: ldr {{w[0-9]+}}, [x0, #16380]
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%1 = add i64 %a, 16380
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32* %2
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ret i32 %3
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}
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; Min un-supported scaled offset
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define i32 @load_breg_immoff_6(i64 %a) {
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; SDAG-LABEL: load_breg_immoff_6
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; SDAG: orr w[[NUM:[0-9]+]], wzr, #0x4000
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; SDAG-NEXT: ldr {{w[0-9]+}}, [x0, x[[NUM]]]
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; FAST-LABEL: load_breg_immoff_6
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; FAST: add [[REG:x[0-9]+]], x0, #4, lsl #12
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; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, 16384
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32* %2
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ret i32 %3
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}
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; Max supported negative offset
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define void @store_breg_immoff_1(i64 %a) {
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; CHECK-LABEL: store_breg_immoff_1
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; CHECK: stur wzr, [x0, #-256]
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%1 = add i64 %a, -256
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%2 = inttoptr i64 %1 to i32*
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store i32 0, i32* %2
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ret void
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}
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; Min not-supported negative offset
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define void @store_breg_immoff_2(i64 %a) {
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; CHECK-LABEL: store_breg_immoff_2
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; CHECK: sub [[REG:x[0-9]+]], x0, #257
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; CHECK-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, -257
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%2 = inttoptr i64 %1 to i32*
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store i32 0, i32* %2
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ret void
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}
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; Max supported unscaled offset
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define void @store_breg_immoff_3(i64 %a) {
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; CHECK-LABEL: store_breg_immoff_3
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; CHECK: stur wzr, [x0, #255]
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%1 = add i64 %a, 255
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%2 = inttoptr i64 %1 to i32*
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store i32 0, i32* %2
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ret void
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}
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; Min un-supported unscaled offset
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define void @store_breg_immoff_4(i64 %a) {
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; CHECK-LABEL: store_breg_immoff_4
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; CHECK: add [[REG:x[0-9]+]], x0, #257
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; CHECK-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, 257
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%2 = inttoptr i64 %1 to i32*
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store i32 0, i32* %2
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ret void
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}
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; Max supported scaled offset
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define void @store_breg_immoff_5(i64 %a) {
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; CHECK-LABEL: store_breg_immoff_5
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; CHECK: str wzr, [x0, #16380]
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%1 = add i64 %a, 16380
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%2 = inttoptr i64 %1 to i32*
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store i32 0, i32* %2
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ret void
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}
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; Min un-supported scaled offset
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define void @store_breg_immoff_6(i64 %a) {
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; SDAG-LABEL: store_breg_immoff_6
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; SDAG: orr w[[NUM:[0-9]+]], wzr, #0x4000
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; SDAG-NEXT: str wzr, [x0, x[[NUM]]]
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; FAST-LABEL: store_breg_immoff_6
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; FAST: add [[REG:x[0-9]+]], x0, #4, lsl #12
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; FAST-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, 16384
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%2 = inttoptr i64 %1 to i32*
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store i32 0, i32* %2
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ret void
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}
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define i64 @load_breg_immoff_7(i64 %a) {
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; CHECK-LABEL: load_breg_immoff_7
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; CHECK: ldr {{x[0-9]+}}, [x0, #48]
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%1 = add i64 %a, 48
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%2 = inttoptr i64 %1 to i64*
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%3 = load i64* %2
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ret i64 %3
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}
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; Flip add operands
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define i64 @load_breg_immoff_8(i64 %a) {
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; CHECK-LABEL: load_breg_immoff_8
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; CHECK: ldr {{x[0-9]+}}, [x0, #48]
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%1 = add i64 48, %a
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%2 = inttoptr i64 %1 to i64*
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%3 = load i64* %2
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ret i64 %3
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}
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; Load Base Register + Register Offset
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define i64 @load_breg_offreg_1(i64 %a, i64 %b) {
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; CHECK-LABEL: load_breg_offreg_1
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; CHECK: ldr {{x[0-9]+}}, [x0, x1]
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i64*
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%3 = load i64* %2
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ret i64 %3
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}
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; Flip add operands
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define i64 @load_breg_offreg_2(i64 %a, i64 %b) {
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; CHECK-LABEL: load_breg_offreg_2
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; CHECK: ldr {{x[0-9]+}}, [x1, x0]
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%1 = add i64 %b, %a
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%2 = inttoptr i64 %1 to i64*
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%3 = load i64* %2
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ret i64 %3
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}
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; Load Base Register + Register Offset + Immediate Offset
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define i64 @load_breg_offreg_immoff_1(i64 %a, i64 %b) {
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; CHECK-LABEL: load_breg_offreg_immoff_1
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; CHECK: add [[REG:x[0-9]+]], x0, x1
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; CHECK-NEXT: ldr x0, {{\[}}[[REG]], #48{{\]}}
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%1 = add i64 %a, %b
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%2 = add i64 %1, 48
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%3 = inttoptr i64 %2 to i64*
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%4 = load i64* %3
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ret i64 %4
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}
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define i64 @load_breg_offreg_immoff_2(i64 %a, i64 %b) {
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; SDAG-LABEL: load_breg_offreg_immoff_2
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; SDAG: add [[REG1:x[0-9]+]], x0, x1
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; SDAG-NEXT: orr w[[NUM:[0-9]+]], wzr, #0xf000
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; SDAG-NEXT: ldr x0, {{\[}}[[REG1]], x[[NUM]]]
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; FAST-LABEL: load_breg_offreg_immoff_2
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; FAST: add [[REG:x[0-9]+]], x0, #15, lsl #12
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; FAST-NEXT: ldr x0, {{\[}}[[REG]], x1{{\]}}
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%1 = add i64 %a, %b
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%2 = add i64 %1, 61440
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%3 = inttoptr i64 %2 to i64*
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%4 = load i64* %3
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ret i64 %4
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}
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; Load Scaled Register Offset
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define i32 @load_shift_offreg_1(i64 %a) {
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; CHECK-LABEL: load_shift_offreg_1
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; CHECK: lsl [[REG:x[0-9]+]], x0, #2
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; CHECK: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
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%1 = shl i64 %a, 2
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32* %2
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ret i32 %3
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}
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define i32 @load_mul_offreg_1(i64 %a) {
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; CHECK-LABEL: load_mul_offreg_1
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; CHECK: lsl [[REG:x[0-9]+]], x0, #2
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; CHECK: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
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%1 = mul i64 %a, 4
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32* %2
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ret i32 %3
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}
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; Load Base Register + Scaled Register Offset
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define i32 @load_breg_shift_offreg_1(i64 %a, i64 %b) {
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; CHECK-LABEL: load_breg_shift_offreg_1
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; CHECK: ldr {{w[0-9]+}}, [x1, x0, lsl #2]
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%1 = shl i64 %a, 2
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%2 = add i64 %1, %b
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%3 = inttoptr i64 %2 to i32*
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%4 = load i32* %3
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ret i32 %4
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}
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define i32 @load_breg_shift_offreg_2(i64 %a, i64 %b) {
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; CHECK-LABEL: load_breg_shift_offreg_2
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; CHECK: ldr {{w[0-9]+}}, [x1, x0, lsl #2]
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%1 = shl i64 %a, 2
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%2 = add i64 %b, %1
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%3 = inttoptr i64 %2 to i32*
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%4 = load i32* %3
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ret i32 %4
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}
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define i32 @load_breg_shift_offreg_3(i64 %a, i64 %b) {
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; SDAG-LABEL: load_breg_shift_offreg_3
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; SDAG: lsl [[REG:x[0-9]+]], x0, #2
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; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x1, lsl #2{{\]}}
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; FAST-LABEL: load_breg_shift_offreg_3
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; FAST: lsl [[REG:x[0-9]+]], x1, #2
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; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
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%1 = shl i64 %a, 2
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%2 = shl i64 %b, 2
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%3 = add i64 %1, %2
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%4 = inttoptr i64 %3 to i32*
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%5 = load i32* %4
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ret i32 %5
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}
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define i32 @load_breg_shift_offreg_4(i64 %a, i64 %b) {
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; SDAG-LABEL: load_breg_shift_offreg_4
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; SDAG: lsl [[REG:x[0-9]+]], x1, #2
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; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
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; FAST-LABEL: load_breg_shift_offreg_4
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; FAST: lsl [[REG:x[0-9]+]], x0, #2
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; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x1, lsl #2{{\]}}
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%1 = shl i64 %a, 2
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%2 = shl i64 %b, 2
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%3 = add i64 %2, %1
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%4 = inttoptr i64 %3 to i32*
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%5 = load i32* %4
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ret i32 %5
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}
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define i32 @load_breg_shift_offreg_5(i64 %a, i64 %b) {
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; SDAG-LABEL: load_breg_shift_offreg_5
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; SDAG: lsl [[REG:x[0-9]+]], x1, #3
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; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
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; FAST-LABEL: load_breg_shift_offreg_5
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; FAST: lsl [[REG:x[0-9]+]], x1, #3
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; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
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%1 = shl i64 %a, 2
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%2 = shl i64 %b, 3
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%3 = add i64 %1, %2
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%4 = inttoptr i64 %3 to i32*
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%5 = load i32* %4
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ret i32 %5
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}
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define i32 @load_breg_mul_offreg_1(i64 %a, i64 %b) {
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; CHECK-LABEL: load_breg_mul_offreg_1
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; CHECK: ldr {{w[0-9]+}}, [x1, x0, lsl #2]
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%1 = mul i64 %a, 4
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%2 = add i64 %1, %b
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%3 = inttoptr i64 %2 to i32*
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%4 = load i32* %3
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ret i32 %4
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}
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|
|
define zeroext i8 @load_breg_and_offreg_1(i64 %a, i64 %b) {
|
|
; CHECK-LABEL: load_breg_and_offreg_1
|
|
; CHECK: ldrb {{w[0-9]+}}, [x1, w0, uxtw]
|
|
%1 = and i64 %a, 4294967295
|
|
%2 = add i64 %1, %b
|
|
%3 = inttoptr i64 %2 to i8*
|
|
%4 = load i8* %3
|
|
ret i8 %4
|
|
}
|
|
|
|
define zeroext i16 @load_breg_and_offreg_2(i64 %a, i64 %b) {
|
|
; CHECK-LABEL: load_breg_and_offreg_2
|
|
; CHECK: ldrh {{w[0-9]+}}, [x1, w0, uxtw #1]
|
|
%1 = and i64 %a, 4294967295
|
|
%2 = shl i64 %1, 1
|
|
%3 = add i64 %2, %b
|
|
%4 = inttoptr i64 %3 to i16*
|
|
%5 = load i16* %4
|
|
ret i16 %5
|
|
}
|
|
|
|
define i32 @load_breg_and_offreg_3(i64 %a, i64 %b) {
|
|
; CHECK-LABEL: load_breg_and_offreg_3
|
|
; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
|
|
%1 = and i64 %a, 4294967295
|
|
%2 = shl i64 %1, 2
|
|
%3 = add i64 %2, %b
|
|
%4 = inttoptr i64 %3 to i32*
|
|
%5 = load i32* %4
|
|
ret i32 %5
|
|
}
|
|
|
|
define i64 @load_breg_and_offreg_4(i64 %a, i64 %b) {
|
|
; CHECK-LABEL: load_breg_and_offreg_4
|
|
; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3]
|
|
%1 = and i64 %a, 4294967295
|
|
%2 = shl i64 %1, 3
|
|
%3 = add i64 %2, %b
|
|
%4 = inttoptr i64 %3 to i64*
|
|
%5 = load i64* %4
|
|
ret i64 %5
|
|
}
|
|
|
|
; Not all 'and' instructions have immediates.
|
|
define i64 @load_breg_and_offreg_5(i64 %a, i64 %b, i64 %c) {
|
|
; CHECK-LABEL: load_breg_and_offreg_5
|
|
; CHECK: and [[REG:x[0-9]+]], x0, x2
|
|
; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]], x1{{\]}}
|
|
%1 = and i64 %a, %c
|
|
%2 = add i64 %1, %b
|
|
%3 = inttoptr i64 %2 to i64*
|
|
%4 = load i64* %3
|
|
ret i64 %4
|
|
}
|
|
|
|
define i64 @load_breg_and_offreg_6(i64 %a, i64 %b, i64 %c) {
|
|
; CHECK-LABEL: load_breg_and_offreg_6
|
|
; CHECK: and [[REG:x[0-9]+]], x0, x2
|
|
; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}x1, [[REG]], lsl #3{{\]}}
|
|
%1 = and i64 %a, %c
|
|
%2 = shl i64 %1, 3
|
|
%3 = add i64 %2, %b
|
|
%4 = inttoptr i64 %3 to i64*
|
|
%5 = load i64* %4
|
|
ret i64 %5
|
|
}
|
|
|
|
; Load Base Register + Scaled Register Offset + Sign/Zero extension
|
|
define i32 @load_breg_zext_shift_offreg_1(i32 %a, i64 %b) {
|
|
; CHECK-LABEL: load_breg_zext_shift_offreg_1
|
|
; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
|
|
%1 = zext i32 %a to i64
|
|
%2 = shl i64 %1, 2
|
|
%3 = add i64 %2, %b
|
|
%4 = inttoptr i64 %3 to i32*
|
|
%5 = load i32* %4
|
|
ret i32 %5
|
|
}
|
|
|
|
define i32 @load_breg_zext_shift_offreg_2(i32 %a, i64 %b) {
|
|
; CHECK-LABEL: load_breg_zext_shift_offreg_2
|
|
; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
|
|
%1 = zext i32 %a to i64
|
|
%2 = shl i64 %1, 2
|
|
%3 = add i64 %b, %2
|
|
%4 = inttoptr i64 %3 to i32*
|
|
%5 = load i32* %4
|
|
ret i32 %5
|
|
}
|
|
|
|
define i32 @load_breg_zext_mul_offreg_1(i32 %a, i64 %b) {
|
|
; CHECK-LABEL: load_breg_zext_mul_offreg_1
|
|
; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
|
|
%1 = zext i32 %a to i64
|
|
%2 = mul i64 %1, 4
|
|
%3 = add i64 %2, %b
|
|
%4 = inttoptr i64 %3 to i32*
|
|
%5 = load i32* %4
|
|
ret i32 %5
|
|
}
|
|
|
|
define i32 @load_breg_sext_shift_offreg_1(i32 %a, i64 %b) {
|
|
; CHECK-LABEL: load_breg_sext_shift_offreg_1
|
|
; CHECK: ldr {{w[0-9]+}}, [x1, w0, sxtw #2]
|
|
%1 = sext i32 %a to i64
|
|
%2 = shl i64 %1, 2
|
|
%3 = add i64 %2, %b
|
|
%4 = inttoptr i64 %3 to i32*
|
|
%5 = load i32* %4
|
|
ret i32 %5
|
|
}
|
|
|
|
define i32 @load_breg_sext_shift_offreg_2(i32 %a, i64 %b) {
|
|
; CHECK-LABEL: load_breg_sext_shift_offreg_2
|
|
; CHECK: ldr {{w[0-9]+}}, [x1, w0, sxtw #2]
|
|
%1 = sext i32 %a to i64
|
|
%2 = shl i64 %1, 2
|
|
%3 = add i64 %b, %2
|
|
%4 = inttoptr i64 %3 to i32*
|
|
%5 = load i32* %4
|
|
ret i32 %5
|
|
}
|
|
|
|
; Make sure that we don't drop the first 'add' instruction.
|
|
define i32 @load_breg_sext_shift_offreg_3(i32 %a, i64 %b) {
|
|
; CHECK-LABEL: load_breg_sext_shift_offreg_3
|
|
; CHECK: add [[REG:w[0-9]+]], w0, #4
|
|
; CHECK: ldr {{w[0-9]+}}, {{\[}}x1, [[REG]], sxtw #2{{\]}}
|
|
%1 = add i32 %a, 4
|
|
%2 = sext i32 %1 to i64
|
|
%3 = shl i64 %2, 2
|
|
%4 = add i64 %b, %3
|
|
%5 = inttoptr i64 %4 to i32*
|
|
%6 = load i32* %5
|
|
ret i32 %6
|
|
}
|
|
|
|
|
|
define i32 @load_breg_sext_mul_offreg_1(i32 %a, i64 %b) {
|
|
; CHECK-LABEL: load_breg_sext_mul_offreg_1
|
|
; CHECK: ldr {{w[0-9]+}}, [x1, w0, sxtw #2]
|
|
%1 = sext i32 %a to i64
|
|
%2 = mul i64 %1, 4
|
|
%3 = add i64 %2, %b
|
|
%4 = inttoptr i64 %3 to i32*
|
|
%5 = load i32* %4
|
|
ret i32 %5
|
|
}
|
|
|
|
; Load Scaled Register Offset + Immediate Offset + Sign/Zero extension
|
|
define i64 @load_sext_shift_offreg_imm1(i32 %a) {
|
|
; CHECK-LABEL: load_sext_shift_offreg_imm1
|
|
; CHECK: sbfiz [[REG:x[0-9]+]], {{x[0-9]+}}, #3, #32
|
|
; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8{{\]}}
|
|
%1 = sext i32 %a to i64
|
|
%2 = shl i64 %1, 3
|
|
%3 = add i64 %2, 8
|
|
%4 = inttoptr i64 %3 to i64*
|
|
%5 = load i64* %4
|
|
ret i64 %5
|
|
}
|
|
|
|
; Load Base Register + Scaled Register Offset + Immediate Offset + Sign/Zero extension
|
|
define i64 @load_breg_sext_shift_offreg_imm1(i32 %a, i64 %b) {
|
|
; CHECK-LABEL: load_breg_sext_shift_offreg_imm1
|
|
; CHECK: add [[REG:x[0-9]+]], x1, w0, sxtw #3
|
|
; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8{{\]}}
|
|
%1 = sext i32 %a to i64
|
|
%2 = shl i64 %1, 3
|
|
%3 = add i64 %b, %2
|
|
%4 = add i64 %3, 8
|
|
%5 = inttoptr i64 %4 to i64*
|
|
%6 = load i64* %5
|
|
ret i64 %6
|
|
}
|
|
|
|
; Test that the kill flag is not set - the machine instruction verifier does that for us.
|
|
define i64 @kill_reg(i64 %a) {
|
|
%1 = sub i64 %a, 8
|
|
%2 = add i64 %1, 96
|
|
%3 = inttoptr i64 %2 to i64*
|
|
%4 = load i64* %3
|
|
%5 = add i64 %2, %4
|
|
ret i64 %5
|
|
}
|
|
|
|
define void @store_fi(i64 %i) {
|
|
; CHECK-LABEL: store_fi
|
|
; CHECK: mov [[REG:x[0-9]+]], sp
|
|
; CHECK: str {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
|
|
%1 = alloca [8 x i32]
|
|
%2 = ptrtoint [8 x i32]* %1 to i64
|
|
%3 = mul i64 %i, 4
|
|
%4 = add i64 %2, %3
|
|
%5 = inttoptr i64 %4 to i32*
|
|
store i32 47, i32* %5, align 4
|
|
ret void
|
|
}
|
|
|
|
define i32 @load_fi(i64 %i) {
|
|
; CHECK-LABEL: load_fi
|
|
; CHECK: mov [[REG:x[0-9]+]], sp
|
|
; CHECK: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
|
|
%1 = alloca [8 x i32]
|
|
%2 = ptrtoint [8 x i32]* %1 to i64
|
|
%3 = mul i64 %i, 4
|
|
%4 = add i64 %2, %3
|
|
%5 = inttoptr i64 %4 to i32*
|
|
%6 = load i32* %5, align 4
|
|
ret i32 %6
|
|
}
|
|
|