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https://github.com/c64scene-ar/llvm-6502.git
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b451f4e376
Thumb-1 only allows SP-based LDR and STR to be word-sized, and SP-base LDR, STR, and ADD only allow offsets that are a multiple of 4. Make some changes to better make use of these instructions: * Use word loads for anyext byte and halfword loads from the stack. * Enforce 4-byte alignment on objects accessed in this way, to ensure that the offset is valid. * Do the same for objects whose frame index is used, in order to avoid having to use more than one ADD to generate the frame index. * Correct how many bits of offset we think AddrModeT1_s has. Patch by John Brawn. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230496 91177308-0d34-0410-b5e6-96231b3b80d8
39 lines
1.1 KiB
LLVM
39 lines
1.1 KiB
LLVM
; RUN: llc -mtriple arm-eabi -disable-fp-elim -filetype asm -o - %s \
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; RUN: | FileCheck -check-prefix CHECK-ARM %s
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; RUN: llc -mtriple thumb-eabi -disable-fp-elim -filetype asm -o - %s \
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; RUN: | FileCheck -check-prefix CHECK-THUMB %s
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; RUN: llc -mtriple arm-darwin -disable-fp-elim -filetype asm -o - %s \
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; RUN: | FileCheck -check-prefix CHECK-DARWIN-ARM %s
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; RUN: llc -mtriple thumb-darwin -disable-fp-elim -filetype asm -o - %s \
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; RUN: | FileCheck -check-prefix CHECK-DARWIN-THUMB %s
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declare void @callee(i32)
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define i32 @calleer(i32 %i) {
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entry:
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%i.addr = alloca i32, align 4
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%j = alloca i32, align 4
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store i32 %i, i32* %i.addr, align 4
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%0 = load i32* %i.addr, align 4
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%add = add nsw i32 %0, 1
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store i32 %add, i32* %j, align 4
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%1 = load i32* %j, align 4
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call void @callee(i32 %1)
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%2 = load i32* %j, align 4
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%add1 = add nsw i32 %2, 1
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ret i32 %add1
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}
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; CHECK-ARM: push {r11, lr}
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; CHECK-ARM: mov r11, sp
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; CHECK-THUMB: push {r7, lr}
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; CHECK-THUMB: add r7, sp, #0
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; CHECK-DARWIN-ARM: push {r7, lr}
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; CHECK-DARWIN-THUMB: push {r7, lr}
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