mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d1cee9b3bc
This partially fixes PR13007 (ARM CodeGen fails with large stack alignment): for ARM and Thumb2 targets, but not for Thumb1, as it seems stack alignment for Thumb1 targets hasn't been supported at all. Producing an aligned stack pointer is done by zero-ing out the lower bits of the stack pointer. The BIC instruction was used for this. However, the immediate field of the BIC instruction only allows to encode an immediate that can zero out up to a maximum of the 8 lower bits. When a larger alignment is requested, a BIC instruction cannot be used; llvm was silently producing incorrect code in this case. This commit fixes code generation for large stack aligments by using the BFC instruction instead, when the BFC instruction is available. When not, it uses 2 instructions: a right shift, followed by a left shift to zero out the lower bits. The lowering of ARM::Int_eh_sjlj_dispatchsetup still has code that unconditionally uses BIC to realign the stack pointer, so it very likely has the same problem. However, I wasn't able to produce a test case for that. This commit adds an assert so that the compiler will fail the assert instead of silently generating wrong code if this is ever reached. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225446 91177308-0d34-0410-b5e6-96231b3b80d8
135 lines
4.1 KiB
LLVM
135 lines
4.1 KiB
LLVM
; RUN: llc -mtriple=arm-none-none-eabi -mcpu=cortex-a15 -o - %s | FileCheck --check-prefix=CHECK-A %s
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; RUN: llc -mtriple=thumb-none-none-eabi -mcpu=cortex-a15 -o - %s | FileCheck --check-prefix=CHECK-A-THUMB %s
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; RUN: llc -mtriple=thumb-apple-none-macho -mcpu=cortex-m3 -o - %s | FileCheck --check-prefix=CHECK-M %s
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declare arm_aapcscc void @bar()
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@bigvar = global [16 x i32] zeroinitializer
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define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" {
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; Must save all registers except banked sp and lr (we save lr anyway because
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; we actually need it at the end to execute the return ourselves).
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; Also need special function return setting pc and CPSR simultaneously.
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; CHECK-A-LABEL: irq_fn:
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; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr}
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; CHECK-A: add r11, sp, #20
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; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}}
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; CHECK-A: bfc sp, #0, #3
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; CHECK-A: bl bar
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; CHECK-A: sub sp, r11, #20
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; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr}
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; CHECK-A: subs pc, lr, #4
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; CHECK-A-THUMB-LABEL: irq_fn:
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; CHECK-A-THUMB: push.w {r0, r1, r2, r3, r4, r7, r12, lr}
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; CHECK-A-THUMB: add r7, sp, #20
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; CHECK-A-THUMB: mov r4, sp
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; CHECK-A-THUMB: bfc r4, #0, #3
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; CHECK-A-THUMB: bl bar
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; CHECK-A-THUMB: sub.w r4, r7, #20
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; CHECK-A-THUMB: mov sp, r4
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; CHECK-A-THUMB: pop.w {r0, r1, r2, r3, r4, r7, r12, lr}
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; CHECK-A-THUMB: subs pc, lr, #4
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; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to
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; appropriate sentinel so no special return needed).
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; CHECK-M-LABEL: irq_fn:
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; CHECK-M: push.w {r4, r10, r11, lr}
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; CHECK-M: add.w r11, sp, #8
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; CHECK-M: mov r4, sp
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; CHECK-M: bfc r4, #0, #3
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; CHECK-M: mov sp, r4
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; CHECK-M: bl _bar
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; CHECK-M: sub.w r4, r11, #8
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; CHECK-M: mov sp, r4
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; CHECK-M: pop.w {r4, r10, r11, pc}
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call arm_aapcscc void @bar()
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ret void
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}
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; We don't push/pop r12, as it is banked for FIQ
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define arm_aapcscc void @fiq_fn() alignstack(8) "interrupt"="FIQ" {
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; CHECK-A-LABEL: fiq_fn:
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; CHECK-A: push {r0, r1, r2, r3, r4, r5, r6, r7, r11, lr}
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; 32 to get past r0, r1, ..., r7
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; CHECK-A: add r11, sp, #32
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; CHECK-A: sub sp, sp, #{{[0-9]+}}
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; CHECK-A: bfc sp, #0, #3
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; [...]
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; 32 must match above
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; CHECK-A: sub sp, r11, #32
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; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r11, lr}
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; CHECK-A: subs pc, lr, #4
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; CHECK-A-THUMB-LABEL: fiq_fn:
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; CHECK-M-LABEL: fiq_fn:
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%val = load volatile [16 x i32]* @bigvar
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store volatile [16 x i32] %val, [16 x i32]* @bigvar
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ret void
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}
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define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" {
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; CHECK-A-LABEL: swi_fn:
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; CHECK-A: push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr}
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; CHECK-A: add r11, sp, #44
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; CHECK-A: sub sp, sp, #{{[0-9]+}}
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; CHECK-A: bfc sp, #0, #3
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; [...]
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; CHECK-A: sub sp, r11, #44
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; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr}
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; CHECK-A: subs pc, lr, #0
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%val = load volatile [16 x i32]* @bigvar
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store volatile [16 x i32] %val, [16 x i32]* @bigvar
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ret void
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}
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define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" {
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; CHECK-A-LABEL: undef_fn:
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; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr}
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; CHECK-A: add r11, sp, #20
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; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}}
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; CHECK-A: bfc sp, #0, #3
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; [...]
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; CHECK-A: sub sp, r11, #20
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; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr}
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; CHECK-A: subs pc, lr, #0
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call void @bar()
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ret void
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}
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define arm_aapcscc void @abort_fn() alignstack(8) "interrupt"="ABORT" {
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; CHECK-A-LABEL: abort_fn:
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; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr}
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; CHECK-A: add r11, sp, #20
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; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}}
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; CHECK-A: bfc sp, #0, #3
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; [...]
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; CHECK-A: sub sp, r11, #20
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; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr}
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; CHECK-A: subs pc, lr, #4
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call void @bar()
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ret void
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}
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@var = global double 0.0
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; We don't save VFP regs, since it would be a massive overhead in the general
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; case.
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define arm_aapcscc void @floating_fn() alignstack(8) "interrupt"="IRQ" {
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; CHECK-A-LABEL: floating_fn:
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; CHECK-A-NOT: vpush
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; CHECK-A-NOT: vstr
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; CHECK-A-NOT: vstm
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; CHECK-A: vadd.f64 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
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%lhs = load volatile double* @var
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%rhs = load volatile double* @var
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%sum = fadd double %lhs, %rhs
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store double %sum, double* @var
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ret void
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}
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