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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243337 91177308-0d34-0410-b5e6-96231b3b80d8
213 lines
5.4 KiB
C++
213 lines
5.4 KiB
C++
//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features such as
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// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_TARGETPARSER_H
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#define LLVM_SUPPORT_TARGETPARSER_H
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// FIXME: vector is used because that's what clang uses for subtarget feature
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// lists, but SmallVector would probably be better
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#include <vector>
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namespace llvm {
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class StringRef;
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// Target specific information into their own namespaces. These should be
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// generated from TableGen because the information is already there, and there
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// is where new information about targets will be added.
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// FIXME: To TableGen this we need to make some table generated files available
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// even if the back-end is not compiled with LLVM, plus we need to create a new
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// back-end to TableGen to create these clean tables.
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namespace ARM {
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// FPU names.
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enum FPUKind {
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FK_INVALID = 0,
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FK_NONE,
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FK_VFP,
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FK_VFPV2,
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FK_VFPV3,
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FK_VFPV3_FP16,
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FK_VFPV3_D16,
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FK_VFPV3_D16_FP16,
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FK_VFPV3XD,
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FK_VFPV3XD_FP16,
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FK_VFPV4,
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FK_VFPV4_D16,
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FK_FPV4_SP_D16,
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FK_FPV5_D16,
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FK_FPV5_SP_D16,
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FK_FP_ARMV8,
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FK_NEON,
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FK_NEON_FP16,
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FK_NEON_VFPV4,
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FK_NEON_FP_ARMV8,
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FK_CRYPTO_NEON_FP_ARMV8,
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FK_SOFTVFP,
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FK_LAST
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};
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// FPU Version
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enum FPUVersion {
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FV_NONE = 0,
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FV_VFPV2,
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FV_VFPV3,
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FV_VFPV3_FP16,
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FV_VFPV4,
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FV_VFPV5
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};
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// An FPU name implies one of three levels of Neon support:
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enum NeonSupportLevel {
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NS_None = 0, ///< No Neon
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NS_Neon, ///< Neon
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NS_Crypto ///< Neon with Crypto
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};
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// An FPU name restricts the FPU in one of three ways:
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enum FPURestriction {
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FR_None = 0, ///< No restriction
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FR_D16, ///< Only 16 D registers
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FR_SP_D16 ///< Only single-precision instructions, with 16 D registers
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};
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// Arch names.
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enum ArchKind {
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AK_INVALID = 0,
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AK_ARMV2,
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AK_ARMV2A,
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AK_ARMV3,
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AK_ARMV3M,
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AK_ARMV4,
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AK_ARMV4T,
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AK_ARMV5T,
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AK_ARMV5TE,
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AK_ARMV5TEJ,
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AK_ARMV6,
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AK_ARMV6K,
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AK_ARMV6T2,
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AK_ARMV6Z,
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AK_ARMV6ZK,
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AK_ARMV6M,
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AK_ARMV6SM,
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AK_ARMV7A,
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AK_ARMV7R,
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AK_ARMV7M,
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AK_ARMV7EM,
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AK_ARMV8A,
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AK_ARMV8_1A,
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// Non-standard Arch names.
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AK_IWMMXT,
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AK_IWMMXT2,
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AK_XSCALE,
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AK_ARMV5,
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AK_ARMV5E,
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AK_ARMV6J,
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AK_ARMV6HL,
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AK_ARMV7,
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AK_ARMV7L,
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AK_ARMV7HL,
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AK_ARMV7S,
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AK_LAST
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};
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// Arch extension modifiers for CPUs.
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enum ArchExtKind : unsigned {
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AEK_INVALID = 0x0,
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AEK_NONE = 0x1,
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AEK_CRC = 0x2,
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AEK_CRYPTO = 0x4,
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AEK_FP = 0x8,
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AEK_HWDIV = 0x10,
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AEK_HWDIVARM = 0x20,
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AEK_MP = 0x40,
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AEK_SIMD = 0x80,
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AEK_SEC = 0x100,
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AEK_VIRT = 0x200,
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// Unsupported extensions.
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AEK_OS = 0x8000000,
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AEK_IWMMXT = 0x10000000,
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AEK_IWMMXT2 = 0x20000000,
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AEK_MAVERICK = 0x40000000,
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AEK_XSCALE = 0x80000000,
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};
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// ISA kinds.
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enum ISAKind {
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IK_INVALID = 0,
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IK_ARM,
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IK_THUMB,
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IK_AARCH64
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};
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// Endianness
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// FIXME: BE8 vs. BE32?
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enum EndianKind {
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EK_INVALID = 0,
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EK_LITTLE,
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EK_BIG
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};
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// v6/v7/v8 Profile
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enum ProfileKind {
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PK_INVALID = 0,
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PK_A,
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PK_R,
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PK_M
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};
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} // namespace ARM
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// Target Parsers, one per architecture.
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class ARMTargetParser {
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static StringRef getHWDivSynonym(StringRef HWDiv);
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static StringRef getFPUSynonym(StringRef FPU);
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static StringRef getArchSynonym(StringRef Arch);
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public:
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static StringRef getCanonicalArchName(StringRef Arch);
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// Information by ID
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static const char * getFPUName(unsigned FPUKind);
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static unsigned getFPUVersion(unsigned FPUKind);
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static unsigned getFPUNeonSupportLevel(unsigned FPUKind);
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static unsigned getFPURestriction(unsigned FPUKind);
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static unsigned getDefaultFPU(StringRef CPU);
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// FIXME: This should be moved to TargetTuple once it exists
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static bool getFPUFeatures(unsigned FPUKind,
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std::vector<const char*> &Features);
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static bool getHWDivFeatures(unsigned HWDivKind,
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std::vector<const char*> &Features);
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static const char * getArchName(unsigned ArchKind);
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static unsigned getArchAttr(unsigned ArchKind);
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static const char * getCPUAttr(unsigned ArchKind);
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static const char * getSubArch(unsigned ArchKind);
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static const char * getArchExtName(unsigned ArchExtKind);
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static const char * getHWDivName(unsigned HWDivKind);
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static const char * getDefaultCPU(StringRef Arch);
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// Parser
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static unsigned parseHWDiv(StringRef HWDiv);
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static unsigned parseFPU(StringRef FPU);
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static unsigned parseArch(StringRef Arch);
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static unsigned parseArchExt(StringRef ArchExt);
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static unsigned parseCPUArch(StringRef CPU);
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static unsigned parseArchISA(StringRef Arch);
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static unsigned parseArchEndian(StringRef Arch);
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static unsigned parseArchProfile(StringRef Arch);
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static unsigned parseArchVersion(StringRef Arch);
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};
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} // namespace llvm
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#endif
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