mirror of
https://github.com/c64scene-ar/llvm-6502.git
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061efcfb3e
Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
3.0 KiB
C++
95 lines
3.0 KiB
C++
//===-- SPUTargetMachine.cpp - Define TargetMachine for Cell SPU ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the Cell SPU target.
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//
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//===----------------------------------------------------------------------===//
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#include "SPU.h"
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#include "SPUTargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/Support/DynamicLibrary.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeCellSPUTarget() {
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// Register the target.
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RegisterTargetMachine<SPUTargetMachine> X(TheCellSPUTarget);
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}
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const std::pair<unsigned, int> *
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SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const {
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NumEntries = 1;
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return &LR[0];
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}
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SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS),
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DataLayout(Subtarget.getTargetDataString()),
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InstrInfo(*this),
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FrameLowering(Subtarget),
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TLInfo(*this),
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TSInfo(*this),
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InstrItins(Subtarget.getInstrItineraryData()) {
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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namespace {
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/// SPU Code Generator Pass Configuration Options.
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class SPUPassConfig : public TargetPassConfig {
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public:
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SPUPassConfig(SPUTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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SPUTargetMachine &getSPUTargetMachine() const {
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return getTM<SPUTargetMachine>();
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}
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virtual bool addInstSelector();
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virtual bool addPreEmitPass();
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};
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} // namespace
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TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new SPUPassConfig(this, PM);
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}
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bool SPUPassConfig::addInstSelector() {
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// Install an instruction selector.
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PM.add(createSPUISelDag(getSPUTargetMachine()));
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return false;
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}
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// passes to run just before printing the assembly
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bool SPUPassConfig::addPreEmitPass() {
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// load the TCE instruction scheduler, if available via
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// loaded plugins
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typedef llvm::FunctionPass* (*BuilderFunc)(const char*);
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BuilderFunc schedulerCreator =
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(BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol(
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"createTCESchedulerPass");
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if (schedulerCreator != NULL)
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PM.add(schedulerCreator("cellspu"));
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//align instructions with nops/lnops for dual issue
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PM.add(createSPUNopFillerPass(getSPUTargetMachine()));
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return true;
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}
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