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https://github.com/c64scene-ar/llvm-6502.git
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38c6b58eec
Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Changes since review (and last commit attempt): - Fixed test failures that were missed due to configuration of local build. (fixes crash.ll and a couple others). - Fixed tests that happened to pass because the local build was on X86 (should fix 2007-12-17-InvokeAsm.ll) - mature-mc-support.ll's should no longer require all targets to be compiled. (should fix ARM and PPC buildbots) - Object output (-filetype=obj and similar) now forces the integrated assembler to be enabled regardless of default setting or -no-integrated-as. (should fix SystemZ buildbots) Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201333 91177308-0d34-0410-b5e6-96231b3b80d8
138 lines
4.6 KiB
LLVM
138 lines
4.6 KiB
LLVM
;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -no-integrated-as < %s | FileCheck %s
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define i64 @test_inline_constraint_r(i64 %base, i32 %offset) {
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; CHECK-LABEL: test_inline_constraint_r:
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%val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 %base, i32 %offset)
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
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ret i64 %val
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}
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define i16 @test_small_reg(i16 %lhs, i16 %rhs) {
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; CHECK-LABEL: test_small_reg:
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%val = call i16 asm sideeffect "add $0, $1, $2, sxth", "=r,r,r"(i16 %lhs, i16 %rhs)
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
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ret i16 %val
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}
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define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) {
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; CHECK-LABEL: test_inline_constraint_r_imm:
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%val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 4, i32 12)
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; CHECK: movz [[FOUR:x[0-9]+]], #4
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; CHECK: movz [[TWELVE:w[0-9]+]], #12
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; CHECK: add {{x[0-9]+}}, [[FOUR]], [[TWELVE]], sxtw
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ret i64 %val
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}
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; m is permitted to have a base/offset form. We don't do that
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; currently though.
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define i32 @test_inline_constraint_m(i32 *%ptr) {
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; CHECK-LABEL: test_inline_constraint_m:
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%val = call i32 asm "ldr $0, $1", "=r,m"(i32 *%ptr)
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; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
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ret i32 %val
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}
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@arr = global [8 x i32] zeroinitializer
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; Q should *never* have base/offset form even if given the chance.
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define i32 @test_inline_constraint_Q(i32 *%ptr) {
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; CHECK-LABEL: test_inline_constraint_Q:
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%val = call i32 asm "ldr $0, $1", "=r,Q"(i32* getelementptr([8 x i32]* @arr, i32 0, i32 1))
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; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
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ret i32 %val
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}
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@dump = global fp128 zeroinitializer
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define void @test_inline_constraint_w(<8 x i8> %vec64, <4 x float> %vec128, half %hlf, float %flt, double %dbl, fp128 %quad) {
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; CHECK: test_inline_constraint_w:
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call <8 x i8> asm sideeffect "add $0.8b, $1.8b, $1.8b", "=w,w"(<8 x i8> %vec64)
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call <8 x i8> asm sideeffect "fadd $0.4s, $1.4s, $1.4s", "=w,w"(<4 x float> %vec128)
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; CHECK: add {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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; CHECK: fadd {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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; Arguably semantically dodgy to output "vN", but it's what GCC does
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; so purely for compatibility we want vector registers to be output.
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call float asm sideeffect "fcvt ${0:s}, ${1:h}", "=w,w"(half undef)
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call float asm sideeffect "fadd $0.2s, $0.2s, $0.2s", "=w,w"(float %flt)
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call double asm sideeffect "fadd $0.2d, $0.2d, $0.2d", "=w,w"(double %dbl)
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call fp128 asm sideeffect "fadd $0.2d, $0.2d, $0.2d", "=w,w"(fp128 %quad)
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; CHECK: fcvt {{s[0-9]+}}, {{h[0-9]+}}
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; CHECK: fadd {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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; CHECK: fadd {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
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; CHECK: fadd {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
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ret void
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}
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define void @test_inline_constraint_I() {
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; CHECK-LABEL: test_inline_constraint_I:
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call void asm sideeffect "add x0, x0, $0", "I"(i32 0)
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call void asm sideeffect "add x0, x0, $0", "I"(i64 4095)
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; CHECK: add x0, x0, #0
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; CHECK: add x0, x0, #4095
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ret void
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}
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; Skip J because it's useless
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define void @test_inline_constraint_K() {
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; CHECK-LABEL: test_inline_constraint_K:
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call void asm sideeffect "and w0, w0, $0", "K"(i32 2863311530) ; = 0xaaaaaaaa
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call void asm sideeffect "and w0, w0, $0", "K"(i32 65535)
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; CHECK: and w0, w0, #-1431655766
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; CHECK: and w0, w0, #65535
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ret void
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}
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define void @test_inline_constraint_L() {
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; CHECK-LABEL: test_inline_constraint_L:
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call void asm sideeffect "and x0, x0, $0", "L"(i64 4294967296) ; = 0xaaaaaaaa
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call void asm sideeffect "and x0, x0, $0", "L"(i64 65535)
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; CHECK: and x0, x0, #4294967296
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; CHECK: and x0, x0, #65535
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ret void
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}
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; Skip M and N because we don't support MOV pseudo-instructions yet.
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@var = global i32 0
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define void @test_inline_constraint_S() {
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; CHECK-LABEL: test_inline_constraint_S:
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call void asm sideeffect "adrp x0, $0", "S"(i32* @var)
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call void asm sideeffect "adrp x0, ${0:A}", "S"(i32* @var)
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call void asm sideeffect "add x0, x0, ${0:L}", "S"(i32* @var)
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; CHECK: adrp x0, var
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; CHECK: adrp x0, var
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; CHECK: add x0, x0, #:lo12:var
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ret void
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}
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define i32 @test_inline_constraint_S_label(i1 %in) {
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; CHECK-LABEL: test_inline_constraint_S_label:
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call void asm sideeffect "adr x0, $0", "S"(i8* blockaddress(@test_inline_constraint_S_label, %loc))
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; CHECK: adr x0, .Ltmp{{[0-9]+}}
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br i1 %in, label %loc, label %loc2
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loc:
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ret i32 0
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loc2:
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ret i32 42
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}
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define void @test_inline_constraint_Y() {
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; CHECK-LABEL: test_inline_constraint_Y:
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call void asm sideeffect "fcmp s0, $0", "Y"(float 0.0)
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; CHECK: fcmp s0, #0.0
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ret void
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}
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define void @test_inline_constraint_Z() {
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; CHECK-LABEL: test_inline_constraint_Z:
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call void asm sideeffect "cmp w0, $0", "Z"(i32 0)
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; CHECK: cmp w0, #0
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ret void
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}
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