mirror of
https://github.com/c64scene-ar/llvm-6502.git
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07786c2f09
Some of the SHA instructions take a scalar i32 as one argument (largely because they work on 160-bit hash fragments). This wasn't reflected in the IR previously, with ARM and AArch64 choosing different types (<4 x i32> and <1 x i32> respectively) which was ugly. This makes all the affected intrinsics take a uniform "i32", allowing them to become non-polymorphic at the same time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200706 91177308-0d34-0410-b5e6-96231b3b80d8
145 lines
5.2 KiB
LLVM
145 lines
5.2 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -mattr=+crypto | FileCheck %s
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; RUN: not llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
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declare <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32>, <4 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32>, <4 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha256h(<4 x i32>, <4 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha1su0(<4 x i32>, <4 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha1m(<4 x i32>, i32, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha1p(<4 x i32>, i32, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha1c(<4 x i32>, i32, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32>, <4 x i32>) #1
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declare i32 @llvm.arm.neon.sha1h(i32) #1
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declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8>) #1
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declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8>) #1
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declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8>, <16 x i8>) #1
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declare <16 x i8> @llvm.arm.neon.aese(<16 x i8>, <16 x i8>) #1
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define <16 x i8> @test_vaeseq_u8(<16 x i8> %data, <16 x i8> %key) {
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; CHECK: test_vaeseq_u8:
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; CHECK: aese {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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; CHECK-NO-CRYPTO: Cannot select: intrinsic %llvm.arm.neon.aese
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entry:
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%aese.i = tail call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %data, <16 x i8> %key)
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ret <16 x i8> %aese.i
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}
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define <16 x i8> @test_vaesdq_u8(<16 x i8> %data, <16 x i8> %key) {
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; CHECK: test_vaesdq_u8:
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; CHECK: aesd {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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entry:
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%aesd.i = tail call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %data, <16 x i8> %key)
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ret <16 x i8> %aesd.i
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}
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define <16 x i8> @test_vaesmcq_u8(<16 x i8> %data) {
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; CHECK: test_vaesmcq_u8:
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; CHECK: aesmc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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entry:
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%aesmc.i = tail call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %data)
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ret <16 x i8> %aesmc.i
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}
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define <16 x i8> @test_vaesimcq_u8(<16 x i8> %data) {
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; CHECK: test_vaesimcq_u8:
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; CHECK: aesimc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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entry:
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%aesimc.i = tail call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %data)
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ret <16 x i8> %aesimc.i
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}
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define i32 @test_vsha1h_u32(i32 %hash_e) {
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; CHECK: test_vsha1h_u32:
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; CHECK: sha1h {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%sha1h1.i = tail call i32 @llvm.arm.neon.sha1h(i32 %hash_e)
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ret i32 %sha1h1.i
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}
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define <4 x i32> @test_vsha1su1q_u32(<4 x i32> %tw0_3, <4 x i32> %w12_15) {
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; CHECK: test_vsha1su1q_u32:
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; CHECK: sha1su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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entry:
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%sha1su12.i = tail call <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32> %tw0_3, <4 x i32> %w12_15)
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ret <4 x i32> %sha1su12.i
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}
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define <4 x i32> @test_vsha256su0q_u32(<4 x i32> %w0_3, <4 x i32> %w4_7) {
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; CHECK: test_vsha256su0q_u32:
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; CHECK: sha256su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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entry:
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%sha256su02.i = tail call <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
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ret <4 x i32> %sha256su02.i
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}
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define <4 x i32> @test_vsha1cq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
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; CHECK: test_vsha1cq_u32:
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; CHECK: sha1c {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
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entry:
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%sha1c1.i = tail call <4 x i32> @llvm.arm.neon.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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ret <4 x i32> %sha1c1.i
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}
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define <4 x i32> @test_vsha1pq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
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; CHECK: test_vsha1pq_u32:
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; CHECK: sha1p {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
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entry:
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%sha1p1.i = tail call <4 x i32> @llvm.arm.neon.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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ret <4 x i32> %sha1p1.i
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}
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define <4 x i32> @test_vsha1mq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
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; CHECK: test_vsha1mq_u32:
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; CHECK: sha1m {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
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entry:
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%sha1m1.i = tail call <4 x i32> @llvm.arm.neon.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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ret <4 x i32> %sha1m1.i
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}
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define <4 x i32> @test_vsha1su0q_u32(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11) {
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; CHECK: test_vsha1su0q_u32:
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; CHECK: sha1su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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entry:
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%sha1su03.i = tail call <4 x i32> @llvm.arm.neon.sha1su0(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11)
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ret <4 x i32> %sha1su03.i
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}
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define <4 x i32> @test_vsha256hq_u32(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) {
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; CHECK: test_vsha256hq_u32:
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; CHECK: sha256h {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s
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entry:
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%sha256h3.i = tail call <4 x i32> @llvm.arm.neon.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
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ret <4 x i32> %sha256h3.i
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}
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define <4 x i32> @test_vsha256h2q_u32(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) {
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; CHECK: test_vsha256h2q_u32:
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; CHECK: sha256h2 {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s
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entry:
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%sha256h23.i = tail call <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
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ret <4 x i32> %sha256h23.i
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}
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define <4 x i32> @test_vsha256su1q_u32(<4 x i32> %tw0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) {
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; CHECK: test_vsha256su1q_u32:
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; CHECK: sha256su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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entry:
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%sha256su13.i = tail call <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32> %tw0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
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ret <4 x i32> %sha256su13.i
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}
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