mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-07 14:33:15 +00:00
ea3d31f580
test cases that will change with the new vector shuffle lowering. This gives us a nice baseline for deltas against. I've checked and removed the cases where there were weird register usage being pinned down, and all of these are extremely pin-pointed tests so fully checking them seems very appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218941 91177308-0d34-0410-b5e6-96231b3b80d8
301 lines
10 KiB
LLVM
301 lines
10 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
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; Verify that each of the following test cases is folded into a single
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; instruction which performs a blend operation.
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define <2 x i64> @test1(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1>
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%or = or <2 x i64> %shuf1, %shuf2
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ret <2 x i64> %or
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}
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define <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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define <2 x i64> @test3(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test3:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
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%or = or <2 x i64> %shuf1, %shuf2
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ret <2 x i64> %or
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}
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define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test4:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test5:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm1, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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define <4 x i32> @test6(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test6:
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; CHECK: # BB#0:
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; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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define <4 x i32> @test7(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test7:
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; CHECK: # BB#0:
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; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; CHECK-NEXT: retq
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%and1 = and <4 x i32> %a, <i32 -1, i32 -1, i32 0, i32 0>
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%and2 = and <4 x i32> %b, <i32 0, i32 0, i32 -1, i32 -1>
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%or = or <4 x i32> %and1, %and2
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ret <4 x i32> %or
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}
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define <2 x i64> @test8(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test8:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%and1 = and <2 x i64> %a, <i64 -1, i64 0>
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%and2 = and <2 x i64> %b, <i64 0, i64 -1>
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%or = or <2 x i64> %and1, %and2
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ret <2 x i64> %or
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}
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define <4 x i32> @test9(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test9:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%and1 = and <4 x i32> %a, <i32 0, i32 0, i32 -1, i32 -1>
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%and2 = and <4 x i32> %b, <i32 -1, i32 -1, i32 0, i32 0>
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%or = or <4 x i32> %and1, %and2
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ret <4 x i32> %or
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}
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define <2 x i64> @test10(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test10:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%and1 = and <2 x i64> %a, <i64 0, i64 -1>
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%and2 = and <2 x i64> %b, <i64 -1, i64 0>
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%or = or <2 x i64> %and1, %and2
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ret <2 x i64> %or
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}
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define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test11:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%and1 = and <4 x i32> %a, <i32 -1, i32 0, i32 0, i32 0>
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%and2 = and <4 x i32> %b, <i32 0, i32 -1, i32 -1, i32 -1>
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%or = or <4 x i32> %and1, %and2
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ret <4 x i32> %or
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}
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define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test12:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm1, %xmm0
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; CHECK-NEXT: retq
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%and1 = and <4 x i32> %a, <i32 0, i32 -1, i32 -1, i32 -1>
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%and2 = and <4 x i32> %b, <i32 -1, i32 0, i32 0, i32 0>
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%or = or <4 x i32> %and1, %and2
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ret <4 x i32> %or
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}
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; Verify that the following test cases are folded into single shuffles.
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define <4 x i32> @test13(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test13:
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; CHECK: # BB#0:
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; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[2,3]
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 1, i32 1, i32 4, i32 4>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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define <2 x i64> @test14(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test14:
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; CHECK: # BB#0:
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; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
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%or = or <2 x i64> %shuf1, %shuf2
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ret <2 x i64> %or
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}
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define <4 x i32> @test15(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test15:
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; CHECK: # BB#0:
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; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,1],xmm0[2,1]
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 1>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 2, i32 1, i32 4, i32 4>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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define <2 x i64> @test16(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test16:
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; CHECK: # BB#0:
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; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
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%or = or <2 x i64> %shuf1, %shuf2
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ret <2 x i64> %or
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}
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; Verify that the dag-combiner does not fold a OR of two shuffles into a single
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; shuffle instruction when the shuffle indexes are not compatible.
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define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test17:
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; CHECK: # BB#0:
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; CHECK-NEXT: xorps %xmm2, %xmm2
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; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,0]
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
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; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,0]
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 2>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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define <4 x i32> @test18(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test18:
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; CHECK: # BB#0:
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; CHECK-NEXT: xorps %xmm2, %xmm2
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; CHECK-NEXT: xorps %xmm3, %xmm3
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; CHECK-NEXT: movss %xmm0, %xmm3
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; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[2,0],xmm2[0,0]
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; CHECK-NEXT: movss %xmm1, %xmm2
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; CHECK-NEXT: orps %xmm3, %xmm2
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; CHECK-NEXT: movaps %xmm2, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 4>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test19:
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; CHECK: # BB#0:
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; CHECK-NEXT: xorps %xmm2, %xmm2
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; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm2[0,0]
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
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; CHECK-NEXT: movdqa %xmm1, %xmm2
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; CHECK-NEXT: pslldq $8, %xmm2
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; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,2]
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; CHECK-NEXT: por %xmm2, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 2, i32 2>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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define <2 x i64> @test20(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test20:
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; CHECK: # BB#0:
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: movq %xmm0, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
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%or = or <2 x i64> %shuf1, %shuf2
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ret <2 x i64> %or
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}
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define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test21:
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; CHECK: # BB#0:
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: pslldq $8, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
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%or = or <2 x i64> %shuf1, %shuf2
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ret <2 x i64> %or
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}
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; Verify that the DAGCombiner doesn't crash in the attempt to check if a shuffle
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; with illegal type has a legal mask. Method 'isShuffleMaskLegal' only knows how to
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; handle legal vector value types.
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define <4 x i8> @test_crash(<4 x i8> %a, <4 x i8> %b) {
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; CHECK-LABEL: test_crash:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <4 x i8> %a, <4 x i8> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
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%shuf2 = shufflevector <4 x i8> %b, <4 x i8> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
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%or = or <4 x i8> %shuf1, %shuf2
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ret <4 x i8> %or
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}
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