mirror of
https://github.com/c64scene-ar/llvm-6502.git
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30b2bdfa73
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77164 91177308-0d34-0410-b5e6-96231b3b80d8
278 lines
8.5 KiB
C++
278 lines
8.5 KiB
C++
//===- Thumb2RegisterInfo.cpp - Thumb-2 Register Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-2 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMSubtarget.h"
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#include "Thumb2InstrInfo.h"
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#include "Thumb2RegisterInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/LLVMContext.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii,
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const ARMSubtarget &sti)
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: ARMBaseRegisterInfo(tii, sti) {
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}
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned SubIdx,
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int Val,
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ARMCC::CondCodes Pred,
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unsigned PredReg) const {
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MachineFunction &MF = *MBB.getParent();
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MachineConstantPool *ConstantPool = MF.getConstantPool();
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Constant *C = ConstantInt::get(Type::Int32Ty, Val);
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unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
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BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
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.addReg(DestReg, getDefRegState(true), SubIdx)
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.addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0);
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}
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static unsigned
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negativeOffsetOpcode(unsigned opcode)
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{
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switch (opcode) {
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case ARM::t2LDRi12: return ARM::t2LDRi8;
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case ARM::t2LDRHi12: return ARM::t2LDRHi8;
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case ARM::t2LDRBi12: return ARM::t2LDRBi8;
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case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
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case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
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case ARM::t2STRi12: return ARM::t2STRi8;
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case ARM::t2STRBi12: return ARM::t2STRBi8;
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case ARM::t2STRHi12: return ARM::t2STRHi8;
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case ARM::t2LDRi8:
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case ARM::t2LDRHi8:
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case ARM::t2LDRBi8:
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case ARM::t2LDRSHi8:
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case ARM::t2LDRSBi8:
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case ARM::t2STRi8:
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case ARM::t2STRBi8:
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case ARM::t2STRHi8:
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return opcode;
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default:
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break;
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}
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return 0;
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}
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static unsigned
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positiveOffsetOpcode(unsigned opcode)
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{
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switch (opcode) {
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case ARM::t2LDRi8: return ARM::t2LDRi12;
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case ARM::t2LDRHi8: return ARM::t2LDRHi12;
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case ARM::t2LDRBi8: return ARM::t2LDRBi12;
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case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
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case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
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case ARM::t2STRi8: return ARM::t2STRi12;
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case ARM::t2STRBi8: return ARM::t2STRBi12;
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case ARM::t2STRHi8: return ARM::t2STRHi12;
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case ARM::t2LDRi12:
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case ARM::t2LDRHi12:
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case ARM::t2LDRBi12:
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case ARM::t2LDRSHi12:
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case ARM::t2LDRSBi12:
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case ARM::t2STRi12:
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case ARM::t2STRBi12:
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case ARM::t2STRHi12:
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return opcode;
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default:
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break;
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}
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return 0;
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}
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static unsigned
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immediateOffsetOpcode(unsigned opcode)
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{
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switch (opcode) {
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case ARM::t2LDRs: return ARM::t2LDRi12;
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case ARM::t2LDRHs: return ARM::t2LDRHi12;
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case ARM::t2LDRBs: return ARM::t2LDRBi12;
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case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
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case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
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case ARM::t2STRs: return ARM::t2STRi12;
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case ARM::t2STRBs: return ARM::t2STRBi12;
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case ARM::t2STRHs: return ARM::t2STRHi12;
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case ARM::t2LDRi12:
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case ARM::t2LDRHi12:
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case ARM::t2LDRBi12:
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case ARM::t2LDRSHi12:
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case ARM::t2LDRSBi12:
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case ARM::t2STRi12:
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case ARM::t2STRBi12:
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case ARM::t2STRHi12:
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case ARM::t2LDRi8:
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case ARM::t2LDRHi8:
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case ARM::t2LDRBi8:
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case ARM::t2LDRSHi8:
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case ARM::t2LDRSBi8:
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case ARM::t2STRi8:
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case ARM::t2STRBi8:
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case ARM::t2STRHi8:
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return opcode;
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default:
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break;
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}
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return 0;
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}
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bool Thumb2RegisterInfo::
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requiresRegisterScavenging(const MachineFunction &MF) const {
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return true;
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}
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int Thumb2RegisterInfo::
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rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc,
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unsigned FrameReg, int Offset) const
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{
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDesc &Desc = MI.getDesc();
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unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
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bool isSub = false;
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// Memory operands in inline assembly always use AddrModeT2_i12
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if (Opcode == ARM::INLINEASM)
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AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
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if (Opcode == ADDriOpc) {
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Offset += MI.getOperand(FrameRegIdx+1).getImm();
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if (Offset == 0) {
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// Turn it into a move.
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MI.setDesc(TII.get(MOVOpc));
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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MI.RemoveOperand(FrameRegIdx+1);
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return 0;
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} else if (Offset < 0) {
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Offset = -Offset;
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isSub = true;
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MI.setDesc(TII.get(SUBriOpc));
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}
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// Common case: small offset, fits into instruction.
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if (ARM_AM::getT2SOImmVal(Offset) != -1) {
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// Replace the FrameIndex with sp / fp
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
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return 0;
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}
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// Otherwise, extract 8 adjacent bits from the immediate into this
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// t2ADDri/t2SUBri.
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unsigned RotAmt = CountLeadingZeros_32(Offset);
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if (RotAmt > 24)
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RotAmt = 24;
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unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
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// We will handle these bits from offset, clear them.
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Offset &= ~ThisImmVal;
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assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
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"Bit extraction didn't work?");
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
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} else {
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// AddrModeT2_so cannot handle any offset. If there is no offset
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// register then we change to an immediate version.
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if (AddrMode == ARMII::AddrModeT2_so) {
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unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
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if (OffsetReg != 0) {
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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return Offset;
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}
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MI.RemoveOperand(FrameRegIdx+1);
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
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Opcode = immediateOffsetOpcode(Opcode);
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AddrMode = ARMII::AddrModeT2_i12;
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}
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// Neon and FP address modes are handled by the base ARM version...
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if ((AddrMode != ARMII::AddrModeT2_i8) &&
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(AddrMode != ARMII::AddrModeT2_i12)) {
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return ARMBaseRegisterInfo::rewriteFrameIndex(MI, FrameRegIdx,
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ARM::t2MOVr, ARM::t2ADDri, ARM::t2SUBri, FrameReg, Offset);
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}
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unsigned NumBits = 0;
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Offset += MI.getOperand(FrameRegIdx+1).getImm();
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// i8 supports only negative, and i12 supports only positive, so
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// based on Offset sign convert Opcode to the appropriate
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// instruction
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if (Offset < 0) {
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Opcode = negativeOffsetOpcode(Opcode);
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NumBits = 8;
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isSub = true;
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Offset = -Offset;
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}
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else {
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Opcode = positiveOffsetOpcode(Opcode);
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NumBits = 12;
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}
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if (Opcode) {
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MI.setDesc(TII.get(Opcode));
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MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
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// Attempt to fold address computation
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// Common case: small offset, fits into instruction.
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unsigned Mask = (1 << NumBits) - 1;
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if ((unsigned)Offset <= Mask) {
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// Replace the FrameIndex with fp/sp
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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ImmOp.ChangeToImmediate((isSub) ? -Offset : Offset);
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return 0;
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}
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// Otherwise, offset doesn't fit. Pull in what we can to simplify
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unsigned ImmedOffset = Offset & Mask;
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ImmOp.ChangeToImmediate((isSub) ? -ImmedOffset : ImmedOffset);
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Offset &= ~Mask;
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}
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}
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return (isSub) ? -Offset : Offset;
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}
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